02-06-2020 05:52 AM
My FPGA clk is 150Mhz,and I want 125mhz to run my soft ip.But i can't do it in xilinx ise.when i create DCM for clk its saying input is of high value and ouput is of low value it can't be done.when i go for pll the minimum input frequency itself 400 Mhz.how can i do.
02-06-2020 07:37 AM
02-20-2020 05:36 AM
my fpga is virtex v and speed is -1.I have 100 as well as 150 mhz but need to have frequencies like 125 mhz,62.5mhz and 62.5 with 180 degree shift.i can't use dcm because if i enter 150 mhz to 125 mhz its not converting what to do
02-20-2020 09:37 AM
My guess is its a findamental thing,
Lets try to expalin what the PLL is doing.
The internals is an oscilator, This oscilator has a minimum and maximum frequency
The output of this oscilator is phase compared to the input which controls the oscilator frequency.
if this was done just like that, the oscilator frequency , call athat Fosc, would be running at the same frequecny as the input.
Now if I was to put a divider on the feedback (M), the comparison would be between Fosc/M and the frequency in , call that Fin.
Now if I divide the frequency in, by say N,
the divider woudl now be comparing Fosc/M with Fin/N.
Assuming Fosc is your output,
Then a quick re arange, Fout = Fin*M/N
So all the tools have to do is find an integer multiple of Fin and Fosc, within the range of the oscilator.
150/125 = 1.2 or 6/5
So the oscilator runs at 150 * 5 = 750 MHz.
your 125 is then this 750 MHz deivided by 6, = 125 MHz.
So now you know how it works,
go check the data sheet , what is the maximum frequency the PLL can run at in the part you have ?