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Observer
Observer
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Registered: ‎10-01-2019

ethernet clk

My FPGA clk is 150Mhz,and I want 125mhz to run my soft ip.But i can't do it in xilinx ise.when i create DCM for clk its saying input is of high value and ouput is of low value it can't be done.when i go for pll the minimum input frequency itself 400 Mhz.how can i do.

 

clk1.jpg
clk2.jpg
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Teacher
Teacher
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Registered: ‎07-09-2009

Its the type and speed of FPGA that dictates the PLL/ DLL limits,

Can you tell us what your fpga is , and what speed grade ?

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Observer
Observer
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Registered: ‎10-01-2019

my fpga is virtex v and speed is -1.I have 100 as well as 150 mhz but need to have frequencies like 125 mhz,62.5mhz and 62.5 with 180 degree shift.i can't use dcm because if i enter 150 mhz to 125 mhz its not converting what to do 

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Teacher
Teacher
219 Views
Registered: ‎07-09-2009

My guess is its a findamental thing,

 

Lets try to expalin what the PLL is doing.

 

The internals is an oscilator, This oscilator has a minimum and maximum frequency

 

The output of this oscilator is phase compared to the input which controls the oscilator frequency. 

   if this was done just like that, the oscilator frequency , call athat Fosc, would be running at the same frequecny as the input.

 

Now if I was to put a divider on the feedback (M), the comparison would be between Fosc/M and the frequency in , call that Fin.

Now if I divide the frequency in, by say N, 

   the divider woudl now be comparing Fosc/M with Fin/N. 

 

Assuming Fosc is your output, 

 

Then a quick re arange, Fout = Fin*M/N 

 

So all the tools have to do is find an integer multiple of Fin and Fosc, within the range of the oscilator.

150/125 = 1.2  or 6/5

 

So the oscilator runs at 150 * 5 = 750 MHz. 

  your 125 is then this 750 MHz deivided by 6, = 125 MHz.

 

So now you know how it works,

    go check the data sheet , what is the maximum frequency the PLL can run at in the part you have ?

 

 

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