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paulplusx
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Registered: ‎01-17-2020

exposed pins for PL I/O on Zedboard

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Hello Everyone,

I am a total noob when it comes to FPGAs and therefore confused about the I/Os available in the Zedboard. I have a few questions:

1. Can HR I/O be understood as I/O coming from the PL side? In that case, are there 200 I/O coming out from PL side (for the CLG484 package)? 

2. Now my question is how many of these I/Os are available to the user in form of mappable physical pins out of the zedboard? I saw a few documents and came to a conclusion that:  On the zedboard we have 68 I/O pins on the FMC and 32 I/O pins via 4 PMODs connectors (8 more pins from another PMOD could be routed via EMIO) and 8 I/O pins (not by default I think, needs some config to convert to IO) from the AMS connector and probably 4 I/O pins from JTAG. So a total 'possibility' of 120 'exposed' I/O pins that can be used simultaneously from all different connectors out of a total of 200 I/O. Am I correct here? 

3.I am also a bit confused about the number of IO pins present in the FMC. As mentioned above (and in the hardware user guide), it says 68 single-ended I/O are available but on page 3 (in the same guide) there is a  picture that shows 82 connections with the PL. I don't understand if it is 68 or 82 I/O pins on the FMC? 

4. Can clock capable pins be used as IO pins?
 
Thank you.

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derekm_
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Registered: ‎01-16-2019

Q1: Yes, 200 High-Range pins in CLG484 Z-7020.

 

Q2. My count is 114:

(a) 74 FMC pins available.

(b) Four PL Pmods = 32 pins. (The PS Pmod doesn't count if you are talking about programmable logic pins. But you can drive those 8 signals using software.)

(c) 8 AMS signals: 4 XADC-GIOx and 4 XADC-ADx.

Note that the JTAG pins don't count.

 

Q3: Some references:

https://reference.digilentinc.com/_media/reference/programmable-logic/zedboard/zedboard-schematic-rev-e1-public.pdf

https://reference.digilentinc.com/_media/reference/programmable-logic/zedboard/fpga_package_pin_to_fmc.pdf

As mentioned above, my count is 74. You should check the schematic to see if any pins have resistors hanging off them (4.7K resistors on I2C signals, for example).

 

Q4. Yes, MRCC and SRCC can be used as normal IO. The Xilinx doc to check for info like this is UG865.

 

I have a ZedBoard but note that I haven't used all the pins in this manner, so I'm only going on the schematic (and knowledge of Zynq and 7-Series FPGAs).

-DerekM

 

 

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derekm_
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Registered: ‎01-16-2019

Q1: Yes, 200 High-Range pins in CLG484 Z-7020.

 

Q2. My count is 114:

(a) 74 FMC pins available.

(b) Four PL Pmods = 32 pins. (The PS Pmod doesn't count if you are talking about programmable logic pins. But you can drive those 8 signals using software.)

(c) 8 AMS signals: 4 XADC-GIOx and 4 XADC-ADx.

Note that the JTAG pins don't count.

 

Q3: Some references:

https://reference.digilentinc.com/_media/reference/programmable-logic/zedboard/zedboard-schematic-rev-e1-public.pdf

https://reference.digilentinc.com/_media/reference/programmable-logic/zedboard/fpga_package_pin_to_fmc.pdf

As mentioned above, my count is 74. You should check the schematic to see if any pins have resistors hanging off them (4.7K resistors on I2C signals, for example).

 

Q4. Yes, MRCC and SRCC can be used as normal IO. The Xilinx doc to check for info like this is UG865.

 

I have a ZedBoard but note that I haven't used all the pins in this manner, so I'm only going on the schematic (and knowledge of Zynq and 7-Series FPGAs).

-DerekM

 

 

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paulplusx
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Registered: ‎01-17-2020

Hello DerekM,

Thank you for your answer and all the linked references. I understood most of what you said but I have a few more questions:

1. What is the difference between a CLK1-M2C_P/CLK0-M2C_P pin and a LA00_P_CC? I know CC means clock capable (which probably means the pin can be used for a clock input or output) but I am not sure of the other one. There are 4 such (CLK1/0) pins.

2. A silly question, can the FMC IO and the four PMODs IO be accessed at the same time through the PL? 

Regards,
Shubham 

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derekm_
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Registered: ‎01-16-2019

1. CLK1-M2C_P/N is how the pin is called in the FMC spec. LA00_P_CC is just the schematic net name in the Zedboard schematic. But in the Xilinx terminology, "CC" = clock capable, "L" = differential, and "P" or "N" indicates the P/N pairs of the differential pins. I guess this is what Digilent are following there. The 7-Series FPGA that the Zynq is based on has 50 pin pairs in each IO bank. All but the top pin and bottom pins are differential pairs (the top and bottom are single-ended only). Note also that clock-capable refers only to inputs on Xilinx FPGAs, not outputs.

2. (No such thing as a silly question ). Yes, you can access (drive/read) all available PL outputs at the same time. Its a fundamental characteristic of FPGAs.

Regards,

-DerekM

paulplusx
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Registered: ‎01-17-2020

1. So you mean to say that there this no difference between the pins labeled CC and the pins labeled CLK? Are both just normal clock-capable pins? Can they be used interchangeably? Is that what you are saying or did I misunderstand you?

The description they give in the link you provided is 'user clock' (for CLK) and 'user-defined clock-capable' (for CC), How are these different?

image.png

2. You said, "clock-capable refers only to inputs on Xilinx FPGAs, not outputs". I didn't quite understand the meaning of this. Isn't the term 'clock capable' means that it can be used for high-speed signals such as clocks as both clock input and clock output to the FPGA (as mentioned here)?

Regards,
Shubham

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bruce_karaffa
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Registered: ‎06-21-2017

Any IO pin may be used as a clock output.  The CC means a clock capable input.  Basically this means that the input buffer on the pin may be connected to the internal clock tree and clock buffers of the FPGA.

paulplusx
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Ohh. I thought that only clock capable pins have the ability to output (not just input) clock 'reliably' (for the same reason you mentioned). So a clock output with frequencies such as 50Mhz-100Mhz can be 'reliably' (with very less clock skew and jitter) generated using any IO pin?

Regards,
Shubham

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derekm_
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Registered: ‎01-16-2019

"So you mean to say that there this no difference between the pins labeled CC and the pins labeled CLK? Are both just normal clock-capable pins? Can they be used interchangeably? Is that what you are saying or did I misunderstand you?

The description they give in the link you provided is 'user clock' (for CLK) and 'user-defined clock-capable' (for CC), How are these different?"

Well, there is no difference in the connection to the Xilinx FPGA. But those pins almost certainly have different definitions and/or usage in the FMC specification. If you're designing an FMC card for the ZedBoard you will definitely have to check the FMC spec, but I have no experience with FMC card design.

 

"Ohh. I thought that only clock capable pins have the ability to output (not just input) clock 'reliably' (for the same reason you mentioned). So a clock output with frequencies such as 50Mhz-100Mhz can be 'reliably' (with very less clock skew and jitter) generated using any IO pin?"

If you want to output well-defined clocks (synchronous to data) from the FPGA, I think you need to use certain primitives called ODDR. At 50+ MHz, I'd say you're getting into that territory. I've had no problem with simpler I2C-style solutions at 25 MHz (Intel SVID protocol) where I didn't bother defining output clocks like that. Some of the programmable logic gurus on here can advise you better (I'm certainly not a PL guru!).