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Adventurer
Adventurer
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Registered: ‎04-14-2015

fifo generator in ila

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Hello All.. I am debugging my project for which i have used an ILA in the project I had created an IP Block and also a counter is in my project now when i try to analyze it using ILA. i am able to see the waveform of counters output and also of the block which i had created through t_data port of MAxi interference of the block. i also want to see the waveform of FIFO ports like dout, rd_en and program empty. i am using the following code for the port declaration but not being able to see the waveform of FIFO ports please someone kindly suggest me what changes do i have to made in order to properly analyze the FIFO signals.. thank you 

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity my_block_v1_0 is
generic (
-- Users to add parameters here

-- User parameters ends
-- Do not modify the parameters beyond this line


-- Parameters of Axi Slave Bus Interface S_AXIS
C_S_AXIS_TDATA_WIDTH : integer := 32;

-- Parameters of Axi Master Bus Interface M_AXIS
C_M_AXIS_TDATA_WIDTH : integer := 32;
C_M_AXIS_START_COUNT : integer := 32
);
port (
-- Users to add ports here
ext_clk : in std_logic;
ext_data : in std_logic_vector(27 downto 0);
full : out std_logic;

rd_en => rd_en_fifo,
dout => ext_data_zeropadded_rd,

prog_empty => prog_empty_fifo;

-- User ports ends
-- Do not modify the ports beyond this line


-- Ports of Axi Slave Bus Interface S_AXIS
-- s_axis_aclk : in std_logic;
-- s_axis_aresetn : in std_logic;
-- s_axis_tready : out std_logic;
-- s_axis_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
-- s_axis_tstrb : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
-- s_axis_tlast : in std_logic;
-- s_axis_tvalid : in std_logic;

-- Ports of Axi Master Bus Interface M_AXIS
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_tstrb : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tready : in std_logic
);
end my_block_v1_0;

architecture arch_imp of my_block_v1_0 is

-- component declaration
-- component my_block_v1_0_S_AXIS is
-- generic (
-- C_S_AXIS_TDATA_WIDTH : integer := 32
-- );
-- port (
-- S_AXIS_ACLK : in std_logic;
-- S_AXIS_ARESETN : in std_logic;
-- S_AXIS_TREADY : out std_logic;
-- S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
-- S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
-- S_AXIS_TLAST : in std_logic;
-- S_AXIS_TVALID : in std_logic
-- );
-- end component my_block_v1_0_S_AXIS;

component my_block_v1_0_M_AXIS is
generic (
C_M_AXIS_TDATA_WIDTH : integer := 32;
C_M_START_COUNT : integer := 32
);
port (
ext_data_zeropadded_rd : in std_logic_vector(31 downto 0);
prog_empty_fifo : in std_logic;
rd_en_fifo : out std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
);
end component my_block_v1_0_M_AXIS;

COMPONENT fifo_generator_0
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;

signal tvalid, tready, reset_fifo, wr_en_fifo, prog_empty_fifo, rd_en_fifo : std_logic;
signal ext_data_zeropadded, ext_data_zeropadded_rd : std_logic_vector(31 downto 0);
constant nibble : std_logic_vector(3 downto 0) := "0000";
signal ext_clk_n : std_logic;
begin

reset_fifo <= not m_axis_aresetn;
wr_en_fifo <= '1';
ext_data_zeropadded <= nibble & ext_data;
ext_clk_n <= not ext_clk;
ext_data_fifo : fifo_generator_0
PORT MAP (
rst => reset_fifo,
wr_clk => ext_clk_n,
rd_clk => m_axis_aclk,
din => ext_data_zeropadded,
wr_en => wr_en_fifo,
rd_en => rd_en_fifo,
dout => ext_data_zeropadded_rd,
full => full,
empty => open,
prog_empty => prog_empty_fifo
);


-- Instantiation of Axi Bus Interface S_AXIS
--my_block_v1_0_S_AXIS_inst : my_block_v1_0_S_AXIS
-- generic map (
-- C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
-- )
-- port map (
-- S_AXIS_ACLK => s_axis_aclk,
-- S_AXIS_ARESETN => s_axis_aresetn,
-- S_AXIS_TREADY => s_axis_tready,
-- S_AXIS_TDATA => s_axis_tdata,
-- S_AXIS_TSTRB => s_axis_tstrb,
-- S_AXIS_TLAST => s_axis_tlast,
-- S_AXIS_TVALID => s_axis_tvalid
-- );

-- Instantiation of Axi Bus Interface M_AXIS
my_block_v1_0_M_AXIS_inst : my_block_v1_0_M_AXIS
generic map (
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_START_COUNT => C_M_AXIS_START_COUNT
)
port map (
ext_data_zeropadded_rd => ext_data_zeropadded_rd,
prog_empty_fifo => prog_empty_fifo,
rd_en_fifo => rd_en_fifo,
M_AXIS_ACLK => m_axis_aclk,
M_AXIS_ARESETN => m_axis_aresetn,
M_AXIS_TVALID => m_axis_tvalid,
M_AXIS_TDATA => m_axis_tdata,
M_AXIS_TSTRB => m_axis_tstrb,
M_AXIS_TLAST => m_axis_tlast,
M_AXIS_TREADY => m_axis_tready

);

-- Add user logic here

-- User logic ends

end arch_imp;

 

 

 

 

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Adventurer
Adventurer
10,386 Views
Registered: ‎04-14-2015

Re: fifo generator in ila

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this is the design file.. with netinsertion method i was getting some error so i choosed to manually insert the ila ip. and i am checking my design step by step.. inside the "my_block" there is a fifo and i want to check the status of the signals of fifo with the help of ILA... all the signals are visible in the waveform but their status is always "0" as you can see it in the file which i uploaded earlier. and this can not be possible because the data which i am getting from the Maxis port the "my_block" is not zero it means that data fifo is accepting data from external counter and passing them to output thrugh Maxis tdata.. 

but fifo's own signals which are prog_empty fifo, full and rd_en these are always zero which i think is due to not properly assigning and declaring them in vhdl code.

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Xilinx Employee
Xilinx Employee
5,534 Views
Registered: ‎09-20-2012

Re: fifo generator in ila

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Hi @sheelanch

 

Please refer to chapter-9 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug908-vivado-programming-debugging.pdf if you need assistance in inserting ILA cores in the design.

Thanks,
Deepika.
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Moderator
Moderator
5,529 Views
Registered: ‎07-01-2015

Re: fifo generator in ila

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Hi @sheelanch,

 

What is the method used to probe these signals?

Try with setup debug to probe the signal and see if it helps.

 

" but not being able to see the waveform of FIFO ports please someone kindly suggest me what changes do i have to made in order to properly analyze the FIFO signals"

 

Do you mean in HW manager you are not seeing the signals getting populated in waveform window?

If so can you try adding the signals manually using "+" sign.

Thanks,
Arpan
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Adventurer
Adventurer
5,521 Views
Registered: ‎04-14-2015

Re: fifo generator in ila

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Hello. @arpansur I had inserted ILA as a separate ip block and connected the probes manually to the input ports of manually. I want to show the ports of FiFo as a separate pins in the the block which I had created and for this I want to write then in main entity so that they can be visible and then I can connect them to the ILA to view the waveform.. I thing in the code which I uploaded here I am not properly assigning and declaring its signals to make them visible .. signlas like dout,rd_en,propgram_empty_fifo and full signals. These are the signals of fifo which I want to see and in hardware manager where ILA's waveform can be seen
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Adventurer
Adventurer
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Registered: ‎04-14-2015

Re: fifo generator in ila

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this is the waveform of my project as you can see i can see the waveform from counter and also the output of block where i had inserted a fifo generator inside it. but i am not able to see the waveform of signals of fifo.. and i think it is because i had not properly initialized them ?? can you please guide me what changes do i have to make in the VHDL code. which i had already posted here....

 

Thank you

ilablock.jpg
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Moderator
Moderator
5,512 Views
Registered: ‎07-01-2015

Re: fifo generator in ila

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Hi @sheelanch,

 

Can you please post the snapshot of the synthesized schematic containing ILA connections?

Also see if you are seeing these signal on clicking "+" sign in the waveform window.

 

Thanks,
Arpan
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1.JPG
Highlighted
Adventurer
Adventurer
10,387 Views
Registered: ‎04-14-2015

Re: fifo generator in ila

Jump to solution

this is the design file.. with netinsertion method i was getting some error so i choosed to manually insert the ila ip. and i am checking my design step by step.. inside the "my_block" there is a fifo and i want to check the status of the signals of fifo with the help of ILA... all the signals are visible in the waveform but their status is always "0" as you can see it in the file which i uploaded earlier. and this can not be possible because the data which i am getting from the Maxis port the "my_block" is not zero it means that data fifo is accepting data from external counter and passing them to output thrugh Maxis tdata.. 

but fifo's own signals which are prog_empty fifo, full and rd_en these are always zero which i think is due to not properly assigning and declaring them in vhdl code.

View solution in original post

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