cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
2,487 Views
Registered: ‎12-25-2015

fpga does not work correctly!

Hi there

I'm working on a project with artix 7 chip. I have two blocks (block1 and block2). when I remove the block2 of my design block1 works correctly, but when I add block2 to my project none of them work correctly anymore. I don't have any timing failure. I'm completely confused. I don't know what I should check. Could you please help me?

 

this is my timing report:


Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false

Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes

 

check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 0 pins that are not constrained for maximum delay.

There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
There are 0 input ports with no input delay specified.

There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
There are 0 ports with no output delay specified.

There are 0 ports with no output delay but user has a false path constraint

There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input

 

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
4.865 0.000 0 26835 0.028 0.000 0 26835 0.000 0.000 0 15592


All user specified timing constraints are met.

 

 

 

 

 

 

and this is utilization report:

Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date : Thu Jun 14 11:18:26 2018
| Host : Sig-90 running 64-bit Service Pack 1 (build 7601)
| Command : report_utilization
| Design : top
| Device : 7a35tftg256-2
| Design State : Fully Placed
------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 8235 | 0 | 20800 | 39.59 |
| LUT as Logic | 7931 | 0 | 20800 | 38.13 |
| LUT as Memory | 304 | 0 | 9600 | 3.17 |
| LUT as Distributed RAM | 24 | 0 | | |
| LUT as Shift Register | 280 | 0 | | |
| Slice Registers | 14955 | 0 | 41600 | 35.95 |
| Register as Flip Flop | 14955 | 0 | 41600 | 35.95 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 22 | 0 | 16300 | 0.13 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+----------------------------+-------+-------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 40 | Yes | - | Set |
| 171 | Yes | - | Reset |
| 58 | Yes | Set | - |
| 14686 | Yes | Reset | - |
+-------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| Slice | 4073 | 0 | 8150 | 49.98 |
| SLICEL | 2829 | 0 | | |
| SLICEM | 1244 | 0 | | |
| LUT as Logic | 7931 | 0 | 20800 | 38.13 |
| using O5 output only | 15 | | | |
| using O6 output only | 6895 | | | |
| using O5 and O6 | 1021 | | | |
| LUT as Memory | 304 | 0 | 9600 | 3.17 |
| LUT as Distributed RAM | 24 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 0 | | | |
| using O5 and O6 | 24 | | | |
| LUT as Shift Register | 280 | 0 | | |
| using O5 output only | 34 | | | |
| using O6 output only | 48 | | | |
| using O5 and O6 | 198 | | | |
| LUT Flip Flop Pairs | 6660 | 0 | 20800 | 32.02 |
| fully used LUT-FF pairs | 664 | | | |
| LUT-FF pairs with one unused LUT output | 5795 | | | |
| LUT-FF pairs with one unused Flip Flop | 5315 | | | |
| Unique Control Sets | 165 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.


3. Memory
---------

+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 29 | 0 | 50 | 58.00 |
| RAMB36/FIFO* | 13 | 0 | 50 | 26.00 |
| RAMB36E1 only | 13 | | | |
| RAMB18 | 32 | 0 | 100 | 32.00 |
| RAMB18E1 only | 32 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 14 | 0 | 90 | 15.56 |
| DSP48E1 only | 14 | | | |
+----------------+------+-------+-----------+-------+


5. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 27 | 27 | 170 | 15.88 |
| IOB Master Pads | 10 | | | |
| IOB Slave Pads | 17 | | | |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 163 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 170 | 0.00 |
| OLOGIC | 0 | 0 | 170 | 0.00 |
+-----------------------------+------+-------+-----------+-------+


6. Clocking
-----------

+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 3 | 0 | 32 | 9.38 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 1 | 0 | 5 | 20.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+


7. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 1 | 0 | 4 | 25.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+------------+-------+---------------------+
| Ref Name | Used | Functional Category |
+------------+-------+---------------------+
| FDRE | 14686 | Flop & Latch |
| LUT2 | 5459 | LUT |
| CARRY4 | 2795 | CarryLogic |
| LUT3 | 1312 | LUT |
| LUT6 | 929 | LUT |
| LUT4 | 800 | LUT |
| SRL16E | 406 | Distributed Memory |
| LUT5 | 244 | LUT |
| LUT1 | 208 | LUT |
| FDCE | 171 | Flop & Latch |
| SRLC32E | 70 | Distributed Memory |
| FDSE | 58 | Flop & Latch |
| FDPE | 40 | Flop & Latch |
| RAMD32 | 36 | Distributed Memory |
| RAMB18E1 | 32 | Block Memory |
| MUXF7 | 22 | MuxFx |
| IBUF | 16 | IO |
| DSP48E1 | 14 | Block Arithmetic |
| RAMB36E1 | 13 | Block Memory |
| RAMS32 | 12 | Distributed Memory |
| OBUF | 11 | IO |
| BUFG | 3 | Clock |
| SRLC16E | 2 | Distributed Memory |
| MMCME2_ADV | 1 | Clock |
| BSCANE2 | 1 | Others |
+------------+-------+---------------------+


9. Black Boxes
--------------

+-----------------+------+
| Ref Name | Used |
+-----------------+------+
| Filter_selector | 1 |
+-----------------+------+


10. Instantiated Netlists
-------------------------

+------------------+------+
| Ref Name | Used |
+------------------+------+
| mult_gen_0 | 24 |
| c_addsub_0 | 16 |
| c_accum_1 | 12 |
| xfft_1 | 1 |
| u_ila_0_CV | 1 |
| fifo_generator_0 | 1 |
| dbg_hub_CV | 1 |
| cmpy_0 | 1 |
| clk_wiz_0 | 1 |
+------------------+------+


report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.223 . Memory (MB): peak = 2022.070 ; gain = 0.000

 

 

 

 

thank a lot.

Tags (3)
0 Kudos
12 Replies
simonpl
Participant
Participant
2,473 Views
Registered: ‎02-11-2015

What does it mean "works correctly" and what "doesn't work"? What do the blocks do? How one is dependent from the other? Have you checked behavioural simulation?

0 Kudos
gin_xil
Adventurer
Adventurer
2,463 Views
Registered: ‎01-19-2018

h.kavian@yahoo.com,

 

You have only questions and NO MEANINGFUL INFO required to answer your questions. :-)

 

0 Kudos
tsjorgensen
Explorer
Explorer
2,458 Views
Registered: ‎09-13-2011

Had a similar head scratching issue back in the days of Virtex IV. Found at last that the input clock was incorrectly terminated and this gave the behaviour that only one of two identical blocks would run correctly. Seemed as well random which block would work. So my advice is to check all basic parameters and if that doesn't reveal anything use ILAs.

2,448 Views
Registered: ‎12-25-2015

@gin_xil

Thanks for your attention.

I apologize for NO MEANINFUL INFO issue. please tell me which information you need. thank you.

0 Kudos
2,444 Views
Registered: ‎12-25-2015

@simonpl

thanks for your answer.

I have two blocks which are completely independent of each other. when I remove block2, the block1 works correctly, but when I add block2 to my design none of them work anymore.
I have simulated my design but when I program the FPGA it does not work.
I apologize for my bad English.

0 Kudos
2,438 Views
Registered: ‎12-25-2015

@tsjorgensen thanks for your attention.

I don't know which parameters you mean. could you please tell me which parameters I should check?

In my board the clock pin is connected to IO_L12N_T1_MRCC_14 pin. I know that it must be connected to P type pin instead of N type. but I can't change it so I have added the below constraint to disable it.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clock/inst/clk_in1_clk_wiz_0]

 

thanks a lot

 

 

0 Kudos
tsjorgensen
Explorer
Explorer
2,425 Views
Registered: ‎09-13-2011

In my case the clock came from a HSTL source but the pin was not configured as a HSTL so can be a good idea to start with the basic stuff like checking if you have the right voltage levels on all pins and banks, the right IO-standards, the right termination schemes etc.
The routing of the clock from a N-MRCC pin is of-course not ideal but I don't think that is the problem, it adds a semi-random delay but if your design isn't synchrounous to the clock source this is normally not a problem.

0 Kudos
2,403 Views
Registered: ‎12-25-2015

@tsjorgensen 

I checked the voltage level, they are correct.

when I running behavioral  simulation signals are correct but when I run post-implementation functional simulation some of signals have X value. could you please tell me why they are X?

thanks a lot.

0 Kudos
tsjorgensen
Explorer
Explorer
2,398 Views
Registered: ‎09-13-2011

Sorry can't help you with that without knowing your complete code.

0 Kudos
1,935 Views
Registered: ‎12-25-2015

 Hi @tsjorgensen

thanks for the comment. could you please tell me some reasons of that?

 

0 Kudos
tsjorgensen
Explorer
Explorer
1,899 Views
Registered: ‎09-13-2011

'X's are often driven by modules and not necessarily due to signal contention, they can be driven when something is not initialized or a result of uninitialized logic combinations. I don't have sufficient information about your system to say if it is one or the other.

0 Kudos
1,860 Views
Registered: ‎12-25-2015

@tsjorgensen

thanks a lot for your attention. I have written some combinational logiccode, and I changed them with sequential equivalent and now it works correctly. Do you know the reason of that? I didn't have any timing problem. I have entered the timing constraints with "constraint wizard".

I know what 'X' means. I don't know why the behavioral simulation and post-implement simulation are not the same. some signals in post-implement simulation have 'X' value but in behavioral simulation they have correct values.

thank you.

0 Kudos