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Observer
Observer
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Registered: ‎10-02-2019

fpga selection

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The caculation of  logic cells in Kintex UltraScale FPGA is different from  Kintex FPGA?

In Kintex FPGA ,the logic cells is 1.6 times CLB LUT. But in UltraScale FPGA,the logic cells is not 1.6 times CLB LUT.

Another question, is it still 6-input LUTs in UltraScale FPGA?

best 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Re: fpga selection

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Hi @philexqklip :

The caculation of  logic cells in Kintex UltraScale FPGA is different from  Kintex FPGA?

  - I suppose you are talking about Kintex Ultrascale and Kintex-7 FPGA.

Yes, in Ultrascale FPGAs, ratio of logic cells to LUTs is not same as that of 7 series FPGAs.

 CLBs ratio US.PNG

In Ultrascale, ratio is 2.18. (318k/145440 ~2.18) You can calculate this by yourself by referring datasheet.

https://www.xilinx.com/support/documentation/selection-guides/ultrascale-fpga-product-selection-guide.pdf 

Consider CLBs and LUTs if you want to know device capacity.

In Ultrascale, each CLB contains one slice with eight 6-input LUTs and sixteen storage elements.

 

Regards,

Priyanka

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Re: fpga selection

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Hi @philexqklip :

The caculation of  logic cells in Kintex UltraScale FPGA is different from  Kintex FPGA?

  - I suppose you are talking about Kintex Ultrascale and Kintex-7 FPGA.

Yes, in Ultrascale FPGAs, ratio of logic cells to LUTs is not same as that of 7 series FPGAs.

 CLBs ratio US.PNG

In Ultrascale, ratio is 2.18. (318k/145440 ~2.18) You can calculate this by yourself by referring datasheet.

https://www.xilinx.com/support/documentation/selection-guides/ultrascale-fpga-product-selection-guide.pdf 

Consider CLBs and LUTs if you want to know device capacity.

In Ultrascale, each CLB contains one slice with eight 6-input LUTs and sixteen storage elements.

 

Regards,

Priyanka

 

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Moderator
Moderator
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Registered: ‎08-08-2017

Re: fpga selection

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Hi @philexqklip 

On addittion to what mentioned by @panantra , 

Though the resources per CLB in 7 series and US/US+ devices are same , but they are advanced as comapared to previous family.

Please refer to the  "Differences from Previous Generations"  section in CLB user guide starting from page 10.

https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf

in short to implement the ASIC equivalent logic  in US/US+ devices , it needs less CLB as compared to 7 series. 

Additionally in US/US+ the term is  "System Logic Cell "  and not the "logic cell" simply.

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