We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for
Did you mean:
Highlighted
Visitor
1,173 Views
Registered: ‎03-11-2018

## frequency resolution of FFT IP core basd on input signal sample rate rather than FFT clock

Hi,

I am am able to compute the FFT using IP core block available in Vivado 2017. However, whatever is the sample rate of input signal to FFT IPcore, the frequency resolution of the FFT is fixed by clock frequency of the FFT. Example

Frequency resolution  = sampling frequency/number of samples

DDS compiler generates sinusoidal frequency 976.56Hz at a clock freq of 1MHz,therefore the sample rate is 1Ms/s. this signal is given as input to the FFT IPcore 9.0 which is clocked at 5MHz with number of samples as 65536. therefore,

Expected frequency resolution = 1MHz/65536, however, measured frequency resolution  =5MHz/65536 in Behavioral simulation (Vivado 2017)

It does not matter what is the clock frequency of DDS compiler, the frequency resolution of the FFT remains at 5MHz/65536. But, in reality the frequency resolution is fixed by sample rate of input signals and the buffer size of FFT.

So, my question is, why in FPGA the frequency resolution is fixed by the clock frequency of FFT rather than sample rate of the input signal.

Help is much appreciated.

Regards,

Subash

Tags (3)
1 Solution

Accepted Solutions
Visitor
1,395 Views
Registered: ‎03-11-2018

## Re: frequency resolution of FFT IP core basd on input signal sample rate rather than FFT clock

I was using in non realtime mode.

I figured out the way to to change the sample rate in FFT IPcore. s_axis_data_tvalid should be triggered at the same sample rate as the input signal and it should be ON for exactly one input clock cycle clock cycle. Basically, if the sample rate of input signal is 20kHZ and clock frequency is 1MHz, then s_axis_data_tvalid should be triggered at 20kHz with the ON time as 1micro seconds.

Rgards
Subash

2 Replies
Explorer
1,143 Views
Registered: ‎09-07-2011

## Re: frequency resolution of FFT IP core basd on input signal sample rate rather than FFT clock

You're right, the FFT clock frequency should not matter.

Are you using it in "Realtime" or "Non-realtime" mode?

You might want non-realtime, so you can load 1 new sample every 5 clocks.

In "realtime" mode, you would have to buffer 65536 samples and then burst them continuously into the FFT without any gaps in the frames.

Visitor
1,396 Views
Registered: ‎03-11-2018