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Observer
Observer
458 Views
Registered: ‎10-13-2007

grouping IDELAYCTRL and ODELAYE3 spread out in multiple banks

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Hi,

i have multiple ODELAYE3s spread out in three banks. also instantiating three instances of IDELAYCTRLs (one for each bank) not able to constrain/group them correctly to get the design to place. (Ultrascale+ device)

the xdc fragment is given below. is there an obvious mistake? (i have tried several ways but no success)

the error message is at the end

regards,

joseph

set_property IODELAY_GROUP bank69_iodelay_grp [get_cells bank69_IDELAYCTRL_inst]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr0_ch1/das[0].ODELAYE3_inst]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr0_ch1/das[1].ODELAYE3_inst]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr0_ch1/ads[0].ODELAYE3_insta]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr0_ch1/ads[0].ODELAYE3_instb]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr0_ch1/ads[1].ODELAYE3_insta]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr0_ch1/ads[1].ODELAYE3_instb]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr1_ch2/ads[0].ODELAYE3_insta]
set_property IODELAY_GROUP bank69_iodelay_grp [get_cells slr1_ch2/ads[0].ODELAYE3_instb]


set_property IODELAY_GROUP bank70_iodelay_grp [get_cells bank70_IDELAYCTRL_inst]
set_property IODELAY_GROUP bank70_iodelay_grp [get_cells slr1_ch2/das[0].ODELAYE3_inst]

set_property IODELAY_GROUP bank71_iodelay_grp [get_cells bank71_IDELAYCTRL_inst]
set_property IODELAY_GROUP bank71_iodelay_grp [get_cells slr1_ch2/das[1].ODELAYE3_inst]
set_property IODELAY_GROUP bank71_iodelay_grp [get_cells slr1_ch2/ads[1].ODELAYE3_instb]
set_property IODELAY_GROUP bank71_iodelay_grp [get_cells slr1_ch2/ads[1].ODELAYE3_insta]

----error message below ----

[Place 30-803] Clock region X4Y6 has 5 IODELAY_GROUPs, either due to locked IO-Delay elements or due to locked IdelayCtrls. List of groups in this clock region:
Group "":
IdelayCtrl inst: bank69_IDELAYCTRL_inst_REPLICATED_0 (Locked to site BITSLICE_CONTROL_X0Y45)
Delay inst: slr0_ch1/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y279)
Delay inst: slr0_ch1/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y280)
Delay inst: slr0_ch1/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y296)
Delay inst: slr0_ch1/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y297)
Delay inst: slr0_ch1/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y286)
Delay inst: slr0_ch1/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y305)
Delay inst: slr1_ch2/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y309)
Delay inst: slr1_ch2/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y310)
Delay inst: slr1_ch2/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y403)
Delay inst: slr1_ch2/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y404)
Delay inst: slr1_ch2/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y333)
Delay inst: slr1_ch2/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y400)
Group "":
IdelayCtrl inst: bank69_IDELAYCTRL_inst_REPLICATED_0_2 (Locked to site BITSLICE_CONTROL_X0Y44)
Delay inst: slr0_ch1/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y279)
Delay inst: slr0_ch1/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y280)
Delay inst: slr0_ch1/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y296)
Delay inst: slr0_ch1/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y297)
Delay inst: slr0_ch1/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y286)
Delay inst: slr0_ch1/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y305)
Delay inst: slr1_ch2/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y309)
Delay inst: slr1_ch2/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y310)
Delay inst: slr1_ch2/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y403)
Delay inst: slr1_ch2/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y404)
Delay inst: slr1_ch2/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y333)
Delay inst: slr1_ch2/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y400)
Group "":
IdelayCtrl inst: bank69_IDELAYCTRL_inst_REPLICATED_0_3 (Locked to site BITSLICE_CONTROL_X0Y47)
Delay inst: slr0_ch1/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y279)
Delay inst: slr0_ch1/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y280)
Delay inst: slr0_ch1/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y296)
Delay inst: slr0_ch1/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y297)
Delay inst: slr0_ch1/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y286)
Delay inst: slr0_ch1/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y305)
Delay inst: slr1_ch2/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y309)
Delay inst: slr1_ch2/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y310)
Delay inst: slr1_ch2/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y403)
Delay inst: slr1_ch2/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y404)
Delay inst: slr1_ch2/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y333)
Delay inst: slr1_ch2/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y400)
Group "bank70_iodelay_grp":
IdelayCtrl inst: bank70_IDELAYCTRL_inst
Delay inst: slr1_ch2/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y333)
Group "":
IdelayCtrl inst: bank71_IDELAYCTRL_inst_REPLICATED_0 (Locked to site BITSLICE_CONTROL_X0Y61)
Delay inst: slr0_ch1/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y279)
Delay inst: slr0_ch1/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y280)
Delay inst: slr0_ch1/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y296)
Delay inst: slr0_ch1/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y297)
Delay inst: slr0_ch1/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y286)
Delay inst: slr0_ch1/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y305)
Delay inst: slr1_ch2/ads[0].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y309)
Delay inst: slr1_ch2/ads[0].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y310)
Delay inst: slr1_ch2/ads[1].ODELAYE3_insta (Locked to site BITSLICE_RX_TX_X0Y403)
Delay inst: slr1_ch2/ads[1].ODELAYE3_instb (Locked to site BITSLICE_RX_TX_X0Y404)
Delay inst: slr1_ch2/das[0].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y333)
Delay inst: slr1_ch2/das[1].ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y400)

[Place 30-99] Placer failed with error: 'Incorrectly locked IODELAY_GROUP instances'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

 

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Observer
Observer
389 Views
Registered: ‎10-13-2007

solved this the hard way

make up a simple design with all ODELAYE3s and a single IDELAYCTRL (and other elements like a BUFG to clock the bits and dummy input pins to set ODELAY values)  in a single file. also a xdc file to reflect the pinout.

this compiles correctly! open the design and find/note the locations of of all IDELAYCTRLs.

in the actual design instantiate the same number and LOC them to the same locations like:

set_property LOC BITSLICE_CONTROL_X0Y51 [get_cells id[0].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y47 [get_cells id[1].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y61 [get_cells id[2].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y62 [get_cells id[3].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y44 [get_cells id[4].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y43 [get_cells id[5].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y45 [get_cells id[6].IDELAYCTRL_inst]

then the design compiles.

there might be a simpler way though....

 

View solution in original post

1 Reply
Observer
Observer
390 Views
Registered: ‎10-13-2007

solved this the hard way

make up a simple design with all ODELAYE3s and a single IDELAYCTRL (and other elements like a BUFG to clock the bits and dummy input pins to set ODELAY values)  in a single file. also a xdc file to reflect the pinout.

this compiles correctly! open the design and find/note the locations of of all IDELAYCTRLs.

in the actual design instantiate the same number and LOC them to the same locations like:

set_property LOC BITSLICE_CONTROL_X0Y51 [get_cells id[0].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y47 [get_cells id[1].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y61 [get_cells id[2].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y62 [get_cells id[3].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y44 [get_cells id[4].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y43 [get_cells id[5].IDELAYCTRL_inst]
set_property LOC BITSLICE_CONTROL_X0Y45 [get_cells id[6].IDELAYCTRL_inst]

then the design compiles.

there might be a simpler way though....

 

View solution in original post