10-10-2018 11:13 PM
I am working with Spartan 6 xc6slx9 which is having communication with CY7C68013A. I am using slave FIFO interface of CYPRESS chip to communicate between host and FPGA, also i am providing external clock to USB chip from FPGA.
The basic idea of USB chip is ,when it have a new data it will send flag to FPGA and then FPGA should assert appropriate signal to receive the data and then deassert the same signal. My problem is , i am unable to send data in bulk. If i do, my terminal gets hanged ( after some time and data is wrong). If i am sending single byte then also after some time terminal gets hanged. I have added extra delay, then also problem is there.
I have attached some part of my code down here.
So what can be issue here.
10-11-2018 04:05 AM
10-11-2018 05:56 AM
I think this is a timing problem. As i am getting signals from CYPRESS and i am asserting or deasserting sig. as procedure requires, i cannot check on waveform(isim).
What can be done here?