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Visitor waxgourd
Visitor
469 Views
Registered: ‎06-08-2018

how to config pins in the HP bank of xc7k325tffg900?

I have a pcb with xc7k325tffg900.The pins in HR banks work well,but the pins in HP banks can't work when they are configured as input or output.The pins in HP  always keep high whatever they are configured as and connected to .For example,When a pin in HP is configured as input and left open,the signal from this pin can be sampled in chipscope and should be logic '0',but in fact ,it is logic '1';when a pin in HP is configured as output and forced to be logic '0',the signal we measured from the pin should be  level low ,but it is level high.
My question:why is this happened?Is there difference  for configuration in Vhdl between pins in HR and pins in HP?Is there special configuration for pins in HP in vhdl or in ucf?Can the pins in HP of xc7k325tffg900 work if vccaux_io is not powered?Another possible reason:the chip is damaged during soldering because of  higher temperature or  longer  time ?

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3 Replies
Xilinx Employee
Xilinx Employee
451 Views
Registered: ‎06-06-2018

Re: how to config pins in the HP bank of xc7k325tffg900?

Hi @waxgourd,

VCCAUXIO powers I/O circuitry of HP banks. powering it is necessary. Please initialiaz the inputs or outputs in your vhdl code.

Regards,

DEEPAK D N

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404 Views
Registered: ‎01-22-2015

Re: how to config pins in the HP bank of xc7k325tffg900?

@waxgourd

     Is there difference  for configuration in Vhdl between pins in HR and pins in HP?
No difference in VHDL.  -but there is a difference in the Vivado XDC constraints file.  You must select an IO standard that is appropriate.  See "Supported I/O Standards and Terminations" in Xilinx document UG471

Please also check the "Recommended Operating Conditions" for Kintex-7 found in Table 2 of Xilinx document DS182.  In particular, note that VCCO(max) for HR banks is 3.465V and for HP banks is only 1.89V.

Mark

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Newbie 2mphtijlc
Newbie
297 Views
Registered: ‎01-01-2019

Re: how to config pins in the HP bank of xc7k325tffg900?

I got this following error in the post-route stage. Here the error is actually shown as 21 cells forming a loop. but the tool provided only 15 cells of 21 cells. Can someone please help 1) how to find all the cells (21 cells)? 2) also how to find combinational loops? REGISTRATION RECORD: HPE0-J55 Braindumps [DRC 23-20] Violation rule (LUTLP-1) Combination loop alert - 21 LUT cells form a combinatorial loop. This can create a race condition.

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