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Visitor
Visitor
735 Views
Registered: ‎06-07-2018

how to design NAND flash controller phy in v7 device

Hi,

I am adding a NAND flash to my design. how design NAND flash controller PHY in Virtex-7 device?

The DQS signal is transfer from flash chip to my FPGA device,along with the data, edge-aligned to the DQS,but i need that data bus signals center-aligned to the DQS edge, how to design my controller PHY for dqs and data bus? 

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Scholar
Scholar
720 Views
Registered: ‎08-07-2014

@wtl121,

 

. how design NAND flash controller PHY in Virtex-7 device?

I don't know.

 

The DQS signal is transfer from flash chip to my FPGA device,along with the data, edge-aligned to the DQS,but i need that data bus signals center-aligned to the DQS edge, how to design my controller PHY for dqs and data bus? 

Use an IDELAY element/s on the incoming data line/s for your desired amount of delay w.r.t your DQS. In this way the data bus signals can be made to be center-aligned with the DQS edge.

There has been many discussions on this in this forum. Search out the relevant posts and read them carefully, specially the explanations from forum member avrum.

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Visitor
Visitor
709 Views
Registered: ‎06-07-2018

WHAT?

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Visitor
Visitor
681 Views
Registered: ‎06-07-2018

SORRY,I didnt see your replay!thx!

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