10-11-2018 02:20 AM
As we know that to execute any looping statement we require few clock cycle, but now i need to execute entire loop in single cycle. first is it possible. if yes how to execute.
always @(posedge clk)
out=(h[k]*x[k]) + out;
always @(posedge clk)
to execute this code we need 4 clock cycles, but i should execute this in single cycle. so any one can help me.
10-11-2018 03:10 AM
I'll have to go back to when I was a learner in verilog a little bit here :)
When you are saying executing in a single clock, are you talking about simulation here?
The advice I would give you is to write it as you want it to work in Hardware after it is synthesized, simulation will look after itself then.
First there should be no need for the initial blocks
When declaring a reg in verilog you can initialize them at the same time.
reg [1:0] k = 2'b00;
you can probably get it all into a single always block
always @(posedge clk)begin
out <= (h[k]*x[k]) + out;
k <= k +1'b1;
k <= 2'b00;
Notice I have used the <= non blocking assignment.
this means that every edge of clk the out register is updated and the 2 bit counter increments. these two do not block each other the simulator will do both in the same simulation time step.
try that and see how you get on.
10-11-2018 10:28 AM
I think the question is "Can I do the entire sum (k=0 to 3) of h[k]*x[k] in one cycle". The answer is yes (but...)
integer k; always @(posedge clk) begin tmp= 0; for (k=0; k<4; k=k+1) begin tmp = tmp + h[k]*x[k]; end out <= tmp; end
In this case (in fact always) you need to pay attention to your blocking vs. non-blocking assignments. The blocking assignments (=) occur immediately - just like they do in software code (C code). The non-blocking assignments (<=) are "deferred" to the end of the "active event queue" - when used in an always @(posedge clk) this has the net effect of having the reg behave like a flip-flop.
Here k and tmp are both temporary variables - they only help define the behavior of "out" from clock to clock - they are not flip-flops, they are not even necessarily wires in the final design...
Of course, it must be stated that this piece of code will be slow (ish). The four multiplications will be done in parallel, but the result of the four multiplications will have to be summed after the multiplications and in the same clock - so the critical path of this piece of code will go through one multiplier and at least two adders...
10-12-2018 09:35 AM
A for loop is absolutely synthesizable in Verilog when done correctly. While I haven't syntax checked the code I posted, I use code like this all the time. It is completely supported by all synthesis tools.