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Adventurer
Adventurer
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Registered: ‎06-05-2020

how to use buffer for RX as input and TX as output

Hello,

 I have one Rx port and one Tx port, now I need one set of input ports for the Rx and one set as Output ports for Tx . Each Rx and Tx ports have differential signals/pins(6 pair), so an Rx port will have 12 pins and Tx port will have 12 pins. And i have to convert differential signals into single ended and vice-versa.

Kindly find the below pin configuration of my code.

module lvds_to_single_ended(
input rx_clk_in_p, // data_clk_p
input rx_clk_in_n, // data_clk_n
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
output tx_clk_out_p, // fb_clk_p
output tx_clk_out_n, // fb_clk_n
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n
);
wire rx_clk_in;
wire tx_clk_out;
wire rx_data_in;
wire tx_data_out;
wire rx_frame_in;
wire tx_frame_out;

endmodule

Please guide me how to map these signals into IBUFDS and OBUF?

Waiting for your response.

Thank you. 

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2 Replies
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Registered: ‎06-21-2017

If you are asking how to instantiate a differential input buffer, open Vivado and go to TOOLS=>LANGUAGE_TEMPLATES=>VERILOG=>DEVICE_PRIMITIVE_INSTANTIATION=>ARTIX7=>IO_COMPONENTS=>INPUT_BUFFERS=>DIFFERENTIAL_BUFFER.  Just instantiate and connect one differential input buffer for each LVDS input pair.  Poke around, you can find the output buffers there too.

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Adventurer
Adventurer
74 Views
Registered: ‎06-05-2020

Hello @bruce_karaffa 

Thank you for your reply.

Can you show me example using my mentioned code?

waiting for your response.

Thank you.

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