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Registered: ‎10-28-2018

iserdes SDR master/slave 6+6 as 12b workaround?

Before I write my own, I was just wondering if someone can confirm that 12b iserdes2 is not possible for SDR, even if using a master6 + slave6 configuration as a work-around? 

I have set up a quick test bench with this configuration and it works perfectly, rotating bits rightwards until it gets to what should be the final alignment.  It then emits the wrong bit pattern.  Attached is the test project for simulation.  The correct alignment is: 12'h4a5 but I get:

1st word = 12'ha54  (1010 0101 0100)

2nd word = 12'h52a  (0101 0010 1010)   // right rotation - seems to be working towards the correct pattern

3rd word = 12'h295  (0010 1001 0101)    // still working, keep rotating....

4th word = 12'h94a  (1001 0100 1010)    // almost done, should get correct word on the next bit-shift.....

5th word = 12'h952  (1001 0101 0010)    // wrong! - should have been 12'h4a5

6th word = 12'h4a9  (0100 1010 1001)    // this is 12h'4a5 plus one bit shift! - don't know why the prev is wrong

I would just write this off as a flaw or technical limitation in their technology - but I thought that the benefit of using their iserdes2 was that it was mapped to hard logic in their i/o block, allowing greater speed. 

Before I write my own, is there any standard verilog implementations for 12b SDR de-serialization that people fall back to as a workaround?

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Registered: ‎10-28-2018

Just want to update my query.  I have written a system verilog bitslip module with parameterized bit width so it can accommodate the missing 12 bit version, as well as other lengths.  Curious as to how much slower it will be compared to the built in Xilinx version.  I had the impression that the Xilinx vers was some or all implemented in silicon.

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