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Observer
Observer
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Registered: ‎03-28-2013

issue about an odd loopback

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hi all
i am using virtex7 FPGA
for some reason,i want to do thing like this.

无标题.png
logic A generate a signal, through IOB, loopback to logic B


can this be realized?  

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Highlighted
Observer
Observer
765 Views
Registered: ‎03-28-2013

i  have solved  this problem

 

use  IOBUF  like this

 

IOBUF IOBUF_inst
(
.O      (signal to logic_B),       // Buffer output
.IO     (d_edge),                     // Buffer inout port (connect directly to top-level port)
.I        (signal from logic_A), // Buffer input
.T       (1'b0)                          // 3-state enable input, high=input, low=output
);

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Highlighted
Observer
Observer
766 Views
Registered: ‎03-28-2013

i  have solved  this problem

 

use  IOBUF  like this

 

IOBUF IOBUF_inst
(
.O      (signal to logic_B),       // Buffer output
.IO     (d_edge),                     // Buffer inout port (connect directly to top-level port)
.I        (signal from logic_A), // Buffer input
.T       (1'b0)                          // 3-state enable input, high=input, low=output
);

View solution in original post

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