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Contributor
Contributor
134 Views
Registered: ‎07-18-2014

issue about the relationship between 7series IO standards and the VCCO

Hi

I am using XC7K325T-FFG900 in my design. I have connected Bank 15 VCCO to 3.3V,and the input signal is 3.3V level too,single-ended,
but the standard of the input signal is set to LVCMOS25,instead of LVCMOS33

as ug381 describes,Spartan-6 can work in this situation,but I have't find the similar comment about 7 series.

 

Will it work with LVCMOS25?


BTW:I'm also not sure whether the LVDS_25 standard is available when the VCCO of the HR bank is 3.3V.
I think it's available as long as the follow three conditions are met,mentioned by Xilinx AR#43989:
1.place a external terminator
2.the VID and VICM are in range
3.VOCM+VOD/2<VCCO+0.2V(this usually can be met when the VCCO is 3.3V)
am I right?

Thanks!

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2 Replies
Xilinx Employee
Xilinx Employee
124 Views
Registered: ‎08-10-2008

回复: issue about the relationship between 7series IO standards and the VCCO

1. Why you don't select the right IOSTANDARD?

I cannot see any reason you need to do so; if must, check Table 9 of DS182, compare the thresholds that LVCMOS33 and LVCMOS25. See if you violates anything that might bring potential risks. It might not damage the device, but it will bring issues such as reliability, bit errors, etc.

2. You can use LVDS_25 but DIFF_TERM is not available if you use Vcco = 3.3V.

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Contributor
Contributor
108 Views
Registered: ‎07-18-2014

回复: issue about the relationship between 7series IO standards and the VCCO

I want to download the same bitstream to the two different type of boards,the VCCO of the two boards is different,so I want to check the issue.

Thanks for your help

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