05-28-2015 02:54 AM
i'm using xc7a200t-2fbg676i , using clock 50mhz to mmcm generate 100mhz signal , send 100mhz to iopin , no load
using scope test this signal , found voh only 2v , next i using 50mhz generate 25mhz , send 25mhz to iopin
found the rising edge time has 10 ns.
05-28-2015 03:08 AM - edited 05-28-2015 03:30 AM
zhongxp wrote ---send 100mhz to iopin , no load using scope test this signal , found voh only 2v ,
What is the bank voltage (VCCO). Is it 3.3V? Also verify whether lvcmos33 properly defined in UCF filr or not.
VCCO must be compatible for all of the inputs and outputs in the same I/O bank. Please make sure that you followed all banking rules as per UG471.
zhongxp wrote---next i using 50mhz generate 25mhz , send 25mhz to iopin found the rising edge time has 10 ns.
Are you using MMCM for clock generation? Please refer chapter-2 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf for more details.
You mentioned no-load. How did you make no load? In case if FPGA assembled on board but receiver IC not mounted then we can not rule out board issues completely.
If possible please run IBIS simulations and verify results. You can download Artix-7 IBIS models from the following link http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/artix-series-fpgas.html
05-28-2015 06:11 AM
LVCMOS outputs default to slow slew rate. You should add SLEW=FAST to your constraints for these outputs. Also if you're not already doing it, use an ODDR to drive the pin rather than trying to directly drive a pin from a clock net.
05-28-2015 06:13 AM
Also, check your oscilloscope bandwidth. It should be at least 300 MHz to properly view a 100 MHz signal. Some scopes have a bandwidth limit feature. If yours has one, make sure it is turned off.
05-28-2015 08:56 PM
vcco is ok , no load mean rcv ic not mounted.
using ibis simulation is ok ,
i'using the same method test on xc4vsx35 , using same scope , signal is ok.