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zarczhang
Visitor
Visitor
4,594 Views
Registered: ‎09-14-2010

mapping error (ERROR:Pack:1107) when trying to use GTX pins as normal IO pins

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when trying to use some pins as normal io pins in FPGA design , the following map error comes out.

 

"ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a    single IOB18 component because the site type selected is not compatible.

   Further explanation:    The component type is determined by the types of logic and the properties and    configuration of the logic it contains. In this case an IO component of type    IOB18 was chosen because the IO contains symbols and/or properties consistent    with single ended I/O usage and a VCCAUX_IO=NORMAL property. Please double    check that the types of logic elements and all of their relevant properties    and configuration options are compatible with the physical site type of the    constraint.

   Summary:    Symbols involved:     BUF symbol "OBUF_X_USB3_TX_DEEMPH<1>" (Output Signal = X_USB3_TX_DEEMPH<1>)     PAD symbol "X_USB3_TX_DEEMPH<1>" (Pad Signal = X_USB3_TX_DEEMPH<1>)    Component type involved: IOB18    Site Location involved: AG1    Site Type involved: OPAD"

 

I am using ise14.6, fpga is xc7v690t-2ffg1761.

 

it looks that this pin is used as GTX pin (MGTXTXN3_114)  on the board schematic.

 

there are also other GTX pins, so can I configure these pins as normal IO pins? if can not be input, can they be configured as output LVCMOS18 or pull down?

 

 

 

 

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012
No, those pins are dedicated GTX pins and they cannot be used a regular IO, neither input nor output.
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muzaffer
Teacher
Teacher
5,669 Views
Registered: ‎03-31-2012
No, those pins are dedicated GTX pins and they cannot be used a regular IO, neither input nor output.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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suresh007
Observer
Observer
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Registered: ‎05-21-2013

hi sir,

 

we got the same error  as pack error 1107

 

the signal chain or routing to the fpga fabric is as follows

 

INSTANTIATE_CLOCK_WIZARD------->ODDR------->OBUF------->SMA_ON_BOARD_KINTEX7(GPIO:Y23)

 

please correct me if I'm wrong

 

the idea is to generate clock & check  on GPIO Y23

 

Please let  me the solution /route map to solve

 

any help will be highly appreciated

 

Regards

Suresh Repudi

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