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Visitor yuanqi_lin
Visitor
225 Views
Registered: ‎09-19-2019

maximum frequency of XC7Z020-1CLG400I

Hi,

I am making a project that a FPGA typed XC7Z020-1CL400I is used to receive a  ADC's datas and go to Real-time computing.The ADC features with 500MHz  conversion rate ,8bits resolution and output interface of LVDS.I failure to find the maximum frequency of PL part ,but only maximum frequency of PS part.Could you please tell me the maximum frequency of PL part and practicability of this plan? What type FPGA can I choose if the  XC7Z020-1CL400I failure to achieve the goal?

Best regards,

lin

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4 Replies
Teacher drjohnsmith
Teacher
219 Views
Registered: ‎07-09-2009

Re: maximum frequency of XC7Z020-1CLG400I

A very good question,

 and unfortunatly , one that is impossible to answer...

The reason.

The PL part, is an FPGA.

FPGAs are user programable, it depends what algorithum you chose, how much parallel processin gyuo are doing, what placment you have , what functions you have.

Where as a CPU, will always run at one frequency, and its IOs are always of one type,  FPGAs are much more flexible.

 

Each chip has a few key numbers in the data sheet that give a good engineer a clue.

For instance, what frequency the PLL/ MMCM can run at,

   what the set up / hold time on an input is,

But even the set up / hold time, is dependent upon the IO type and the placment of the registers in your design,

 

The only way to tell, even if you have years of experiance,  is to do quick dummy designs of your key parts,

   see what works what dosnt. what design is to big , needs to be improved, different algorithums

 

 

 

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Visitor yuanqi_lin
Visitor
209 Views
Registered: ‎09-19-2019

Re: maximum frequency of XC7Z020-1CLG400I

Hi,

Thank you! But you ignore some thing.Plase look at the picture about virtex-5.In fact ,FPGA datasheets include the frequency,but the XC7Z020-1CLG400I belong to SOC don't incloud this.Why?

Best regards,

liin

virtex-5.png

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Scholar u4223374
Scholar
184 Views
Registered: ‎04-26-2015

Re: maximum frequency of XC7Z020-1CLG400I

@yuanqi_lin 

They're not included because those values are not really useful. They're the absolute maximum that it's possible to achieve, but not values that any user is actually likely to achieve with reasonably complex logic.

On an XC7Z020, I'd probably target 100MHz by default, with 200MHz being achievable without too much effort and 250 - 300MHz being achievable with a lot of effort. To process 500MHz data, assuming you can get it into the chip*, you could process four samples in parallel at 125MHz, which would be an easy speed to achieve.

(*) Depends on the interface. The XC7Z020 should be able to achieve >800Mbps inputs with DDR LVDS. If the ADC has a single LVDS link giving you 8-bit 500MHz data then that'll be running at 4Gbps - much faster than the XC7Z020 can manage (it'll require a chip like the XC7Z015 that has high-speed transceivers). If the ADC has a lot of slower LVDS links (eg. eight 500Mbps links) then that'll be fine.

 

Teacher drjohnsmith
Teacher
177 Views
Registered: ‎07-09-2009

Re: maximum frequency of XC7Z020-1CLG400I

Your are right , and oh so so wrong.

Your question is an old one,

  it all comes from the days of PLD's which wer every simple , and full y specified so yo ucoudl work out how fats they would go.

  then came CPLDs, and the FPGAs..

   For a few years a few decades back, FPGA  companies tried using standard circuits in the FPGA to give an idea as to how fast it was.

This had a few problems,

  a) It rapidly fell into a war among the companies as to how fast a companies chip was , saying "look here".

       companies started making special bits of circiuits to make the bench marks faster to gain points.

           making th ecomaprisons to real circuits meaningless.

b) companies used differnet bench marks between chips and each other,

      maenain git was impossible to compare between chips

c) people did not read or understand the very resticted conditoins used to get the results,

        so it was impossible to use the results in real desings, leading to may re deisngs needed.

d) Look at the data yo show as an example , its typicaly , in this situation ,

e) how do you account in the ref circuits for thigs like IO speed, different IO's ,

    how do you account for instance for say a muliplier, do yo show the DSP blco or th elogic,

           in say an FFT , I'd need lots of DSP, how do you account for the routing between DSP's  what abotu across DSP in different lines of the FPGA.

 

All these and many more numbrs are in the data sheet, and are gauranteed,

but your current application and design is unlikely to bear any resembelance to the next one or my current one,

 

The only way is to try / experiment / learn

its called engineering I'm afraid,

  

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