02-26-2016 09:35 AM
I used Iserdeses of a Zynq 7000. first I can not used Iserdes in DDR mode, to solve this problem I decided to use 2 iserdes in the SDR mode. how to invert data in the second iserdes? i need to a invert bufio to do this.
02-26-2016 09:39 AM
Do you mean use the falling edge clock? The data is not inverted in DDR, it is the data changing at both the rising and fallings clock edges.
02-26-2016 10:09 AM
I used a iserdes in the DDR mode with posedge clock and without idelay. in this mode of data_rate the pattern of data was disturbed. Voyager in the following link have an idea to use iserdes in the sdr:
"To compensate the inversion done of the sdin_n signal, you will need to invert the bits produced by the ISERDES connected to it"Voyager said. when i used inversion in the my verilog code, this error " [place 30-642] placement validity check: failed to find legal placement ..." was showen. when i remove inversion of data input to iserdes this error was removed. how to use inversion of data ?
02-26-2016 01:15 PM
You need to invert the parallel data coming out of the ISERDES. It is not possible to invert data between the pin and the ISERDES.
02-26-2016 07:55 PM
thanks. I need to invert input data to iserdes. How to used an iserdes in the sdr mode to handle ddr input?
02-26-2016 08:31 PM
Do you have differential input like LVDS? That was necessary in order to use the IBUFDS_DIFF_OUT as noted in the thread you mentioned. For single-ended input like LVCMOS, you don't have this option. It was not necessary to invert the input data. Inversion was just a side-effect of using the IBUFDS with differential outputs. The IBUFDS_DIFF_OUT just provided a routing option to reach a second ISERDES. For single-ended inputs, you don't have this path available because it would belong to an adjacent IOB. For a single-ended input you need to figure out how to use one input to the ISERDES, either in DDR mode or by doubling the clock and using SDR mode. Whether or not clock doubling is possible depends on the frequency.
02-26-2016 08:53 PM
many thanks. yes i used a LVDS input and i used IBUFDS_DIFF_OUT. I used _p side to an iserdes and _N side to another. if _N side is inverted version of the _P side, I need to invert _N side to get true data.
02-27-2016 08:28 AM - edited 02-27-2016 08:29 AM
That's OK. To get true data, invert the outputs (parallel) of the ISERDES on the n side. You cannot invert the input to the ISERDES because the ISERDES requires a direct dedicated path from the IBUFDS_DIFF_OUT and it is not possible to insert an inverter. Inverting the parallel outputs is equivalent to inverting the serial input. It just needs to happen after the ISERDES where you can do it in the FPGA fabric.