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368 Views
Registered: ‎07-31-2019

no content in ILA core

Im trying to generate PWM signals. Why its not showing any contents' in ILA core?

Differential clock(sysclk_p and n) is 100Mhz and clk_out1 is 100mhz.

Contraint file

## Clock Signal
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports sysclk_n]
set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports sysclk_p]


## Buttons
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports reset_n]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports decrease_duty]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports increase_duty]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports cpu_resetn]

## LEDs
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports PWM_OUT]

set_property MARK_DEBUG true [get_nets {counter_debounce_reg[11]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[25]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[21]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[12]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[3]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[19]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[17]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[9]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[10]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[24]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[26]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[15]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[4]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[1]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[20]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[0]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[23]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[16]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[8]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[22]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[13]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[14]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[5]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[6]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[27]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[2]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[7]}]
set_property MARK_DEBUG true [get_nets {counter_debounce_reg[18]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[7]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[4]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[3]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[1]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[0]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[5]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[2]}]
set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[6]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[6]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[7]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[5]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[2]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[1]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[0]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[4]}]
set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[3]}]
set_property MARK_DEBUG true [get_nets decrease_duty_IBUF]
set_property MARK_DEBUG true [get_nets increase_duty_IBUF]
set_property MARK_DEBUG true [get_nets PWM_OUT_OBUF]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk_gen/inst/clk_out]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 28 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {counter_debounce_reg[0]} {counter_debounce_reg[1]} {counter_debounce_reg[2]} {counter_debounce_reg[3]} {counter_debounce_reg[4]} {counter_debounce_reg[5]} {counter_debounce_reg[6]} {counter_debounce_reg[7]} {counter_debounce_reg[8]} {counter_debounce_reg[9]} {counter_debounce_reg[10]} {counter_debounce_reg[11]} {counter_debounce_reg[12]} {counter_debounce_reg[13]} {counter_debounce_reg[14]} {counter_debounce_reg[15]} {counter_debounce_reg[16]} {counter_debounce_reg[17]} {counter_debounce_reg[18]} {counter_debounce_reg[19]} {counter_debounce_reg[20]} {counter_debounce_reg[21]} {counter_debounce_reg[22]} {counter_debounce_reg[23]} {counter_debounce_reg[24]} {counter_debounce_reg[25]} {counter_debounce_reg[26]} {counter_debounce_reg[27]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {DUTY_CYCLE[0]} {DUTY_CYCLE[1]} {DUTY_CYCLE[2]} {DUTY_CYCLE[3]} {DUTY_CYCLE[4]} {DUTY_CYCLE[5]} {DUTY_CYCLE[6]} {DUTY_CYCLE[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {counter_PWM_reg__0[0]} {counter_PWM_reg__0[1]} {counter_PWM_reg__0[2]} {counter_PWM_reg__0[3]} {counter_PWM_reg__0[4]} {counter_PWM_reg__0[5]} {counter_PWM_reg__0[6]} {counter_PWM_reg__0[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list decrease_duty_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list increase_duty_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list PWM_OUT_OBUF]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

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Highlighted
Teacher
Teacher
350 Views
Registered: ‎07-09-2009

does it simulate without the ILA ?
can you share your code as an attatchment
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
308 Views
Registered: ‎07-31-2019

`timescale 1ns / 1ps


module PWM_Signals
(

input sysclk_p,
input sysclk_n,
input reset_n,
input cpu_resetn,
input increase_duty,
input decrease_duty,
output PWM_OUT );

wire clk;
wire locked;
wire slow_clk_enable; // slow clock enable signal for debouncing FFs
reg[31:0] counter_debounce=0;// counter for creating slow clock enable signals
wire tmp1,tmp2,duty_inc;// temporary flip-flop signals for debouncing the increasing button
wire tmp3,tmp4,duty_dec;// temporary flip-flop signals for debouncing the decreasing button
reg[7:0] counter_PWM=0;// counter for creating 10Mhz PWM signal
reg[7:0] DUTY_CYCLE=128; // initial duty cycle is 50%

always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
counter_debounce <= 0;
end else begin
if (counter_debounce>=100000000) begin
counter_debounce <= 0;
end else begin
counter_debounce <= counter_debounce + 1;
end
end
end

assign slow_clk_enable = counter_debounce == 100000000 ?1:0;
DFF_PWM PWM_DFF1(clk,reset_n,slow_clk_enable,increase_duty,tmp1);
DFF_PWM PWM_DFF2(clk,reset_n,slow_clk_enable,tmp1, tmp2);
assign duty_inc = tmp1 & (~ tmp2) & slow_clk_enable;
// debouncing FFs for decreasing button
DFF_PWM PWM_DFF3(clk,reset_n,slow_clk_enable,decrease_duty, tmp3);
DFF_PWM PWM_DFF4(clk,reset_n,slow_clk_enable,tmp3, tmp4);
assign duty_dec = tmp3 & (~ tmp4) & slow_clk_enable;
// vary the duty cycle using the debounced buttons above
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)begin
DUTY_CYCLE=128;
end else begin
if(duty_inc==1 && DUTY_CYCLE <= 255) begin
DUTY_CYCLE <= DUTY_CYCLE + 1;// increase duty cycle by 10%
end else if(duty_dec==1 && DUTY_CYCLE>=1) begin
DUTY_CYCLE <= DUTY_CYCLE - 1;//decrease duty cycle by 10%
end
end
end

always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0) begin
counter_PWM <= 0;
end else begin
if(counter_PWM >= 255) begin
counter_PWM <= 0;
end else begin
counter_PWM <= counter_PWM + 1;
end
end
end
assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;




clk_wiz_0 clk_gen (
.clk_out(clk),
.clk_in1_p(sysclk_p),
.clk_in1_n(sysclk_n),
.resetn(reset_n),
.locked(locked)
);

endmodule

// Debouncing DFFs for push buttons on FPGA
module DFF_PWM(clk,rst,en,D,Q);
input clk,rst,en,D;
output reg Q;
always @(posedge clk or negedge rst)
begin
if (rst == 0) begin
Q <= 0;
end else if(en == 1) // slow clock enable signal
Q <= D;
end
endmodule




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Highlighted
Teacher
Teacher
292 Views
Registered: ‎07-09-2009

please share your code as an attachment,
please include your test bench as well,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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