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tvgod2000
Observer
Observer
536 Views
Registered: ‎07-27-2018

no driven PLLCLK of DCM2PLL

Hi, I have a problem with my PLLCLK of DCM2PLL. I'm using Spartan6 SP605 evaluation board.

Error does not occur but CLKPLL will not be driven. I'm sorry if it was too basic a question.

I'm looking forward to your answer. here is code.

module COARSE(GCLK, PULSE, RESET, Q, CLKPLL);
  
 input GCLK, PULSE, RESET;
 
 output [5:0]Q;
 output CLKPLL;
 
 reg [5:0]Q;
 
   wire CLKFB_IN, GCLK_IBUFG, CLK90_BUF, GND, CLK0_BUFG, CLK0_BUFG_O;
 
 always @(posedge CLKPLL)
 if (RESET) Q <= 0;
 else if (PULSE) Q <= Q + 1'b1;
 
   assign GND = 0;
 
   IBUFG GCLK_IBUFG_INST (.I(GCLK),
                           .O(GCLK_IBUFG));
         
 BUFG CLK0_BUFG_INST (.I(CLK0_BUFG),
         .O(CLK0_BUFG_O));
         
         
   DCM_SP DCM_INST (.CLKFB(CLK0_BUFG_O),
                 .CLKIN(GCLK_IBUFG),
                 .CLK0(CLK0_BUFG),
                 .CLK90(CLK90_BUFG),
                 .DSSEN(GND),
                 .PSCLK(GND),
                 .PSEN(GND),
                 .PSINCDEC(GND),
                 .RST(GND),
                 .CLKDV(),
                 .CLKFX(),
                 .CLKFX180(),
                 .CLK2X(),
                 .CLK2X180(),
                 .CLK180(),
                 .CLK270(),
                 .LOCKED(),
                 .PSDONE(),
                 .STATUS());
 
   defparam DCM_INST.CLK_FEEDBACK = "2X";
   defparam DCM_INST.CLKDV_DIVIDE = 2.0; 
   defparam DCM_INST.CLKFX_DIVIDE = 1; 
   defparam DCM_INST.CLKFX_MULTIPLY = 2;
   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
   defparam DCM_INST.CLKIN_PERIOD = 37.037;
   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
   defparam DCM_INST.PHASE_SHIFT = 0;
   defparam DCM_INST.STARTUP_WAIT = "FALSE";

 
 PLL_BASE PLL_INST(.CLKFBOUT(CLKFBOUT),
  .CLKOUT0(CLKPLL),
  .CLKOUT1(),
  .CLKOUT2(),
  .CLKOUT3(),
  .CLKOUT4(),
  .CLKOUT5(),
  .RST(),
  .CLKFBIN(CLKFBOUT),
  .CLKIN(CLK90_BUFG),
  .LOCKED());
 
 defparam PLL_INST.CLKOUT0_PHASE = 0;
 defparam PLL_INST.CLKOUT0_DUTY_CYCLE = 0.5;
 defparam PLL_INST.CLKOUT0_DIVIDE = 2;
 defparam PLL_INST.CLKFBOUT_PHASE = 0;
 defparam PLL_INST.CLKFBOUT_MULT = 15;
 defparam PLL_INST.DIVCLK_DIVIDE = 2;
 defparam PLL_INST.CLKIN_PERIOD = 18.518;
 defparam PLL_INST.COMPENSATION = "DCM2PLL";
 defparam PLL_INST.BANDWIDTH = "OPTIMIZED";
 defparam PLL_INST.CLK_FEEDBACK = "CLKFBOUT";

endmodule

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1 Reply
jheslip
Xilinx Employee
Xilinx Employee
488 Views
Registered: ‎06-30-2010

@tvgod2000 sorry i dont understand this question:

 

"Error does not occur but CLKPLL will not be driven. I'm sorry if it was too basic a question." Do you mean no SW error?

 

The more details you can give on the problem the better we will be able to help.

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