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Registered: ‎12-06-2018

number of clock domains for ADC & DAC interface


I am currently working on a university project involving the nexys video board. The on board chip is an Artix-7 with a LPC FMC interface.

My design includes a high speed ADC and DAC, and my question is regarding the clock sycronization.

In order to determine my clock design I need to know how many different clock domains are needed.

There is not enough clock connections on the FMC to drive ADC and DAC directly, so I will be using an on board clock generator.

The ADC has 1 differential clock input and 1 LVDS clock output.

The DAC has 2 differential clock inputs and a differential syncronization input.

The data going to the FPGA board from the ADC needs to by syncronized so the ADC output clock is going back to the FPGA board as well.

The data to the DAC also needs to be syncronized hence the DAC syncronization input.

I need to determine the reference clock input to the clock generator.

Option 1

Use an XO as reference and send one of the generator outputs back to the FPGA

Option 2

Use a clock from the FPGA as reference clock?

If option 2 do I still need to send one of the generator outputs back to the FPGA?

I have 3 clock connections on the FMC, but I would really prefer only to use 2 so I can use the 3rd one for data transfer/SPI/enable signals etc.


Regards Michelle

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Registered: ‎01-22-2015

Re: number of clock domains for ADC & DAC interface

Hi Michelle,

Welcome to the Xilinx Forum.  I hope things are going well for you at Danmarks Tekniske Universitet.

     I need to determine the reference clock input to the clock generator.
I understand you have a board with ADC and DAC that you are interfacing to a Digilent Nexys Video board with Artix-7.   It is always recommended that the main clock for ADCs and DACs be a low-jitter clock.  Without low-jitter, the Effective-Number-Of-Bits (ENOB) for these devices could be degraded. Clocks generated by your Artix-7 FPGA will have jitter that is approximately 100ps Pk-Pk. However, clocks generated by a crystal oscillator can have jitter as low as 1ps Pk-Pk. You will find discussion in <this> long post about how jitter affects ENOB for an ADC.

So, the answer to your question is to use your “Option 1”. That is, you should use a crystal oscillator (XO) to create the main clock for the ADC and for the DAC.

With regards to clock domains, you will have at least two.  The data-clock coming from the ADC will produce one clock-domain in the FPGA where you will capture the data coming from the ADC.  Along with the data that you send to the DAC, you will also send a data-clock that is generated by the FPGA.  This data-clock for the DAC will produce a clock-domain in the FPGA.