05-11-2016 08:33 AM
I'm using some XC7Z030's odelaye2, to delay signals. I instantiated the idelayctrl too. The clock frequency is 200 MHz. Accordingly DS182
"Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics" The step resolution should be 78.5 ps but it is twice this value, 157 ps. Therefore the max delay I can introduce is about 5 ns.
This is my instantion:
m_odelay: ODELAYE2
generic map(
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "ODATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
ODELAY_TYPE => "VARIABLE",
ODELAY_VALUE => 0,
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA")
port map(
CNTVALUEOUT => s_odelay_value,
DATAOUT => s_tick,
C => i_rx_usr_clk,
CE => s_CE,
CINVCTRL => s_CINVCTRL,
CLKIN => s_CLKIN,
CNTVALUEIN => s_CNTVALUEIN,
INC => s_INC,
LD => s_LD,
LDPIPEEN => s_LDPIPEEN,
ODATAIN => i_delay_data,
REGRST => s_REGRST);
What I'm doing wrong? It's not the first time I'm using an odelay.
05-19-2016 02:13 AM
05-11-2016 01:45 PM
Hello @abaxor,
As per datasheet below, the tap resolution when REFCLK _FREQUENCY is 200 MHz is 78 ps.
http://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf (page #52)
Can you share complete design here to have a look where exactly delay values went wrong?
05-12-2016 01:17 AM
05-13-2016 12:18 AM
Hello @abaxor,
I have checked the design. ODELAYE2 component is used in restrig_fine.vhdl and deltrig_fine.vhdl files. Did you observe same behavior with both of the files? It seems that you haven't shared testbench to verify the functionality. Can you check if you are getting correct delays in simulation (using testbench) before moving to hardware verification?
05-13-2016 11:44 AM
05-19-2016 02:13 AM
05-19-2016 02:15 AM
@abaxor Thanks for sharing the information for other forum users benefit.
06-24-2019 12:07 PM
Tom,
Because I am facing the same issue like you did, could you please to share us more information about how to solve this issue?
You mentioned that "I solved the problem, by extending the reset."
What reset did you extended? is idelayctrl's reset?
Thank you very much in advance!