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Voyager
Voyager
548 Views
Registered: ‎08-16-2018

output clock control

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I need to control an output clock from an Artix-7 (stop it to have a specific number of clocks).

That's not how I would do it, but that's how it's specified...

I'm thinking of a BUFMRCE block then a standard OBUF. There will be serial data (1 bit) synchronous to that clock.

Any thoughts?

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Scholar
Scholar
541 Views
Registered: ‎05-21-2015

@johnvivm,

I create most of my output clocks using an ODDR primitive.  That allows me to duplicate the operation of the current clock, but with good fidelity.  It is a recommended solution.

Is this the sort of thing you are trying to do?

I'm a bit confused by your reference to a BUFGMRCE.  Are you talking instead about a clock going to the output drivers of the chip?

Dan

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Scholar
Scholar
542 Views
Registered: ‎05-21-2015

@johnvivm,

I create most of my output clocks using an ODDR primitive.  That allows me to duplicate the operation of the current clock, but with good fidelity.  It is a recommended solution.

Is this the sort of thing you are trying to do?

I'm a bit confused by your reference to a BUFGMRCE.  Are you talking instead about a clock going to the output drivers of the chip?

Dan

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Voyager
Voyager
527 Views
Registered: ‎08-16-2018
That's actually a good idea, DDR doesn't mean data has to be! I was stuck in the box this time.
Yes, the clock is to come out of the FPGA
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