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helmutforren
Scholar
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Registered: ‎06-23-2014

proc_sys_reset not working for Power Up

Surely I'm doing something wrong.  I'm using proc_sys_reset and want my KC705 board to configure from SPI, and my fabric get reset, merely upon Power Up.  However, after programming the config flash and power cycling, the diagnostic LED's simply stay bright (same as not configured).  I believe config has happened, but not reset.  If I press SW14 (prog), which I believe causes a SECOND configuration, the diagnostic LED's start blinking after 35 seconds (config time) as anticipated.  I believe both config and reset have happened.  (Note in addition, I must wait 35 seconds after power on before pressing SW14 in order for things to work, so it's like I have to wait for the first config before doing the second config.)

 

    wire sys_rst; //////////////////////////////////// This signal used to reset fabric
wire sys_clk_i; IBUFGDS #( .DIFF_TERM("FALSE") ) CL_iob ( .I(SYSCLK_P), .IB(SYSCLK_N), .O(sys_clk_i) ); proc_sys_reset_0 proc_sys_reset ( .mb_reset(), .bus_struct_reset(), .peripheral_reset (sys_rst), .interconnect_aresetn(), .peripheral_aresetn(), .slowest_sync_clk (sys_clk_i), .ext_reset_in (0), .aux_reset_in(0), .mb_debug_sys_rst (0), .dcm_locked (1) );
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3 Replies
austin
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Registered: ‎02-27-2008

h,

 

The KC705 has a xc7v325t device, which has no hardened ARM core, so the only processor reset is one you add by placing a MicroBlaze in your design.  So, before configuration, there is no processor reset signal.  There is only Prog_b (the pushbutton), or by powering on, you trigger a configuration in the mode specified by the MODE pins automatically.  Once configured, the processor reset only reset the MicroBlaze: it will not reconfigure the device.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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helmutforren
Scholar
Scholar
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Registered: ‎06-23-2014

SOLVED:  It wasn't a proc_sys_reset program at all.  It was that the KC705 won't configure at all while the JTAG USB cable is plugged in.  Remove that cable, and all works as expected.

 

Also...

 

@austin thanks for your answer, but I believe you misunderstood my situation.  I was using proc_sys_reset to generate the "rst" signal going to my FPGA fabric, with no MicroBlaze at all.  I think that *should*, and now *is* working.  It's probably not necessary at all, and I'm open to revised advice. (I wasn't wanting it to reconfigure the device.  I was only wanting it to output a signal that I could use to reset my fabric.  It was the first "power on reset" I found when researching.  I later found EOS and GSR.)

 

Right now, my test case has STARTUPE2 signal EOS feeding proc_sys_reset, and that in turn generating a "rst" I use everywhere (with buffering).  Downstream as well are a couple MMCM's, and for logic needing it, I logical OR the "rst" with the MMCM ~locked.  My manager wants me to move all the MMCM ~locked in front of all logic, not just logic that interacts with those subordinate clocks. 

 

If I do that, then I'll have STARTUPE2 signal EOS feeding proc_sys_reset, then that feeding reset to all the MCMM's, then combining all their ~locked to get a "rst" for all my logic (with buffering).

 

What might you suggest, instead, @austin ?  Omit proc_sys_reset and use just EOS and MMCM ~locked?  I read about GSR but don't know where to find it yet.  I've seen glbl.GSR, but not sure how to make that syntax correct.

 

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hpoetzl
Voyager
Voyager
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Registered: ‎06-24-2013

Hey @helmutforren,

 

I read about GSR but don't know where to find it yet.

GSR as well as GTS is an input to STARTUPE2.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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