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Newbie
Newbie
6,474 Views
Registered: ‎10-14-2014

reference clock input problem in kintex-7 transceiver

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Dear all,

      when I use the 7series FPGA  GTX/GTH transceivers IP core(v3.3), I found that it requires a pair of system clocks(sysclk_p/sysclk_n) and a pair of clocks called q0_clk1_gtrefclk_pad_p_in/q0_clk1_gtrefclk_pad_n_in. My source clock is 200Mhz.And I customized the reference clock is 200Mhz in the ip core wizard. My problem is how to drive the two pairs of clocks.

Best regards

Liao

 

 

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Xilinx Employee
Xilinx Employee
10,513 Views
Registered: ‎02-06-2013

Hi

 

You can find the description of the clocks from the below doc

 

http://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_3/pg168-gtwizard.pdf

 

The q0_clk1_gtrefclk_pad_p_in/q0_clk1_gtrefclk_pad_n_in clocks are transceiver reference clocks as defined in the UG476 while the sysclk is used for the additional logic which is used to implement the logic in FPGA.

 

The UG476 describes only about the gtrefclk as this is only clock required for the transceiver.

 

This clock should be provided from an external reference oscillator and directly to the dedicated transceiver clock pins.

 

The sysclk which is used for the FPGA logic can be sourced from the internal clocks or external clock.

 

Hope this clears your query.

 

 

Regards,

Satish

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Moderator
Moderator
6,469 Views
Registered: ‎01-16-2013
Hi,

This is differential clock input _p and _n.
You can lock both _p and _n clock to the associated pins.
And create_clock for _P port.

Use IBUFGDS as clock buffer.

Thanks,
Yash
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Newbie
Newbie
6,465 Views
Registered: ‎10-14-2014

Thanks for your reply.

But my problem is which pair of clocks is the reference clock(200Mhz). I can't find the descroption of the two pairs of clocks in  the user guide (ug476).

Thank you. 

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Xilinx Employee
Xilinx Employee
10,514 Views
Registered: ‎02-06-2013

Hi

 

You can find the description of the clocks from the below doc

 

http://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_3/pg168-gtwizard.pdf

 

The q0_clk1_gtrefclk_pad_p_in/q0_clk1_gtrefclk_pad_n_in clocks are transceiver reference clocks as defined in the UG476 while the sysclk is used for the additional logic which is used to implement the logic in FPGA.

 

The UG476 describes only about the gtrefclk as this is only clock required for the transceiver.

 

This clock should be provided from an external reference oscillator and directly to the dedicated transceiver clock pins.

 

The sysclk which is used for the FPGA logic can be sourced from the internal clocks or external clock.

 

Hope this clears your query.

 

 

Regards,

Satish

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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Newbie
Newbie
6,431 Views
Registered: ‎10-14-2014

Hi,

Thank you!! I followed your advice and solved this problem. Your help is important to a freshman. Thanks for your reply!

 

Best wishes

 

liao

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