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Visitor arakkim
Registered: ‎08-21-2018

relationship between FIT rate and process technology

Hi. currently i'm testing with SEM IP. I have read UG116, Device Reliability Report.

I have a question about relationship between FIT rate and process tech.

the table Table 1-19, 1-20 shows that FIT rate gets better with the deep-sub micron. 

At 180nm to 130nm, the failure rate is twice as bad, and the 90nm process is much better, and the FIT rate continue to improve with the deep sub-micron technology. I'm quite confused with this result.

I learned that smaller then 65nm, they uses planar MOSFET with high-k metal gate  or high doping, UTB-SOI and so on.

and then 14nm uses FinFET. it is all about improve gate control-ability and reduce leakage..

which factor makes improve FIT rate? 

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Registered: ‎09-17-2018

Re: relationship between FIT rate and process technology



I taught a 6 part course to IC designers starting in 2002.  I talked about how to improve FIT in spite of the technology trend of increasing FIT.  UG116 is a testament to my leadership, and the hard work of hundreds of design engineers.  No longer with Xilinx, I am happy say that now that Moore's Law is over, and Xilinx RIF'd me (no need for my skills it seems), I can go on and perform my magic for others.



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