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Registered: ‎01-22-2015

report_synchronizer_mtbf

Xilinx ug835 says that "The report_synchronizer_mtbf command reports mean time between failures (MTBF) of

each clock domain crossing (CDC) synchronizer...".  However, the command is supported only for Ultrascale devices and not for 7-series devices.

 

I have found calculations for synchronizer MTBF (due to metastability).  However, they require values for flop parameters:

   tau = settling time constant of the flop

   tW = (roughly) time window of susceptability for the flop

 

Q1: Are these flop parameters found in the Xilinx docs or must I call my Xilinx FAE to get them?

 

In <this post> gszakacs says that "fabric flops" are better for building synchronizers than "SRL flops" and that setting ASYNC_REG properly ensures that the "fabric flops" are used.   In <this post>, avrumw suggests that the "IDDR flops" can be used to make the perfect 2-flop synchronizer. 

 

Q2: Does Avrum's comment imply that the "IDDR flops" are better for building synchronizers than the "fabric flops"?

 

 

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Registered: ‎01-22-2015

Why is Xilinx reluctant to provide flip-flop parameters (tau, tW) that are related to metastability?  Is this proprietary information or is there concern that we will use them improperly? 

 

I found old Xilinx App Notes (XAPP077 and XAPP094) that describe use of these parameters for calculating MTBF.  Are the formulas found in these App Notes no longer valid?

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Registered: ‎01-22-2015

Lack of responses to my post suggests that I’ve hit on a forbidden topic. So, I’ll wrap things up by saying that I found very interesting reading about synchronizer MTBF in papers by Ran Ginosar – especially his 2011 tutorial publish in IEEE CS, which can be found <here>.

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Advisor
Advisor
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Registered: ‎10-10-2014

In this post I got a reply from @muzaffer where he tells me to contact my FAE for an excel study spreadsheet, that partly answers your question I guess.

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Registered: ‎01-22-2015

Thanks Ronny!  Its good to hear from you.

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Guide
Guide
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Registered: ‎01-23-2009

Q2: Does Avrum's comment imply that the "IDDR flops" are better for building synchronizers than the "fabric flops"?

 

I actually have no idea if the IDDR flip-flops themselves are better or worse than the fabric flip-flops for metastability resolution. I assume they are about the same (SRLs are worse because they are not actually flip-flops - they are some kind of latch based shift register). My reason for suggesting that the IDDR is better is that the two flip-flops in the IDDR in SAME_EDGE_PIPELINED mode are part of the same cell - there is effectively no routing between them. This means that the entire clock period is available for metastability resolution...

 

Avrum

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Registered: ‎01-22-2015

Thank you, Avrum!

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