12-09-2018 06:36 AM
I am using the selectIO IP core to capture a LVDS output from ADC. My processor is spartan6 lx45t, and I am using ISE14.7.
My design always fail at "Map" stage, and I have such error:
ERROR:Place:1318 - User has over-constrained component
Inst_adc_data_in/inst_select_io_in/bufio2_inst. There are no placeable sites
that satisfy the user constraints. Please review the user constraints on the
driver component and the load components of
I have read throuth some posts which say this may becuase that the bufio2_inst is not is the same band of the LVDS clk pins. But I have already added such constrains to my design:
NET "P_I_DCLK_P" LOC = L15;
NET "P_I_DCLK_N" LOC = L16;
INST "Inst_adc_data_in/inst_select_io_in/bufio2_inv_inst" AREA_GROUP = "pblock_1";
INST "Inst_adc_data_in/inst_select_io_in/bufio2_inst" AREA_GROUP = "pblock_1";
AREA_GROUP "pblock_1" RANGE=SLICE_X30Y50:SLICE_X59Y80;
AREA_GROUP "pblock_1" RANGE=DSP48_X1Y13:DSP48_X1Y19;
AREA_GROUP "pblock_1" RANGE=RAMB16_X2Y26:RAMB16_X3Y38;
AREA_GROUP "pblock_1" RANGE=RAMB8_X2Y26:RAMB8_X3Y39;
But still it dosen't work. Could you tell me how to fix this problem? Thanks!
12-09-2018 11:24 AM
The block in question has a BUFIO2 instance in it. An AREA_GROUP is defined separately for each type of resource in the design - you have defined the regions for SLICE, DSP and RAMs, but not for clock components. Take a look at UG625, under the AREA_GROUP property (the first property in Chapter 3) and you will see all the definitions. Specifically there is a BUFIO2_XnYn - since you haven't specified this, the AREA_GROUP has no BUFIO2 sites in it.
Generally it is not recommended to put I/O or clocking resources in an AREA_GROUP. If possible, move the BUFIO2 out of the module you are trying to place in an AREA_GROUP - leave it at the top level of the design, and only put the lower level module in the AREA_GROUP.
12-09-2018 05:49 PM
Thanks for the quick reply,
If possible, move the BUFIO2 out of the module you are trying to place in an AREA_GROUP - leave it at the top level of the design, and only put the lower level module in the AREA_GROUP.
Yes, that is what I want to do, but the BUFIO2 inst is automaticlly generated by the selectIO IP core generator, not by me, I am not sure whether it will be OK if I make some changes after the Core is generated.
The CLK pin is not changable because the PCB has already been manufactoried, so if I still want to use the selectIO IP core, I have to manually put the BUFIO2 inst within the same bank of the CLK pin.
If I delete the CLK pin definition in the ucf file, then ISE will put it in bank 2 (R8 and T8), not in bank 1(L15 and L16) as actually is. I think this behavior is very unfriendly to users, because normally the clk pin is decieded first by some hardware engineers, then the ISE should locate the BUFIO inst according to the decieded clk pin, not inversely.
12-10-2018 09:14 AM
Re-read the first part of my last response.
The message is saying that the AREA_GROUP you defined does not have any BUFIO2 sites in it, and it is correct; since your area group definition does not contain
AREA_GROUP "pblock_1" RANGE=BUFIO2_XnYn;
there are no BUFIO2 cells in your AREA_GROUP.
So you have two choices - define the BUIFO2 range in your AREA_GROUP or remove the BUFIO2 from the instance that you are placing in the area group. You only addressed the second of these two choices - removing the BUFIO2 cell from the module; since this comes from an IP, this is not a practical solution. So you need to investigate what happens if you add the BUFIO2_XnYn range.
As for what bank things are in, once you fix this problem, you may end up with a different one (illegal connectivity between an IBUF and a BUFIO2), but for the moment, the problem is your AREA_GROUP definition.