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javad_2040
Observer
Observer
734 Views
Registered: ‎05-09-2018

signal with High-z value can't update in process block!

Hi.

I design a system that contain SDRAM and spartan6 FPGA. I wrote SDRAM-Controller code for handle the SDRAM. In my code the defualt value of the SDRAM_DQ is High-z. My problem is that i send my data to SDRAM and recieved it but the received value is always 0xFF...FF.

the code is :

process(state_reg,Data_in)
begin
        SDRAM_DQ <= (others => 'z');
        .
        .
        .
	case state_reg is
               when wr0 =>
                      SDRAM_DQ <= Data_in;
                      .
                      .
                      .
         end case;
end process;

data_out <= SDRAM_DQ;

seems the SDRAM_DQ signal wouldn't update and always has High-z value.

is anybody known that what is the problem?

Regards,          

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jheslip
Xilinx Employee
Xilinx Employee
700 Views
Registered: ‎06-30-2010

have you tried simulating?

Does the case statement ever get into the other cases?
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