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Participant
Participant
1,322 Views
Registered: ‎11-15-2017

simulate sub-block ip

Hello,

 

I have a block design with an IP sub-block. I have been managing my test benches separately and wiring up all of the interconnected IP modules manually.  I want to simulate the ip integrator sub-block contents directly from within vivado.  It seems that I can create a test bench that instantiates the sub-block wrapper.  When I do this however, the sub modules are not found.

 

How do I manage my simulation environment more efficiently? 

 

I generate output products OOC per IP.

I have enabled "Include all design sources for simulation" in the simulation project advanced settings tab.

 

Here is an imagesource_window.png

 

How do I tell Vivado where to find the library elements that it created?  They seem to only show up under "Block Sources" in the libaries tab in the source window.  (As opposed to Design Sources).

 

Thanks,

Nick

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Moderator
Moderator
1,310 Views
Registered: ‎05-31-2017

Hi @mxdsgnl,

 

Please check the below AR regarding this and follow the steps as mentioned in it

https://www.xilinx.com/support/answers/60703.html

 

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Participant
Participant
1,306 Views
Registered: ‎11-15-2017

Hello @shameera

 

Thanks for following up.  I followed those steps prior to posting my message.  In fact, the image in my original post shows what happens when I follow those steps.  The path to the sub-block IP wrappers are not know to the simulation engine.

 

I am able to manually locate the files on the drive and use TCL to add them to the simulation set.  However, changing the contents of the block diagram (i.e. replicating some blocks and removing some other blocks) will create wrappers with new names and break the original paths.

 

Thanks,

Nick

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Moderator
Moderator
1,304 Views
Registered: ‎05-31-2017

Hi @mxdsgnl,

 

Did you set the Hierarchy Update to Automatic Update, Manual Compile Order before simulating ?

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Participant
Participant
1,300 Views
Registered: ‎11-15-2017

yes:

automatic_update_manual_compile_order.png

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Participant
Participant
1,233 Views
Registered: ‎11-15-2017

Hi @shameera,

 

I notice that if I export the .prj file that Vivado includes the path of each .v file required for simulation.  Any thoughts as to why I this information isn't also used during the instantiation of each module?

 

Are you able to recreate an issue like this? 

 

Thanks,

Nick

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Moderator
Moderator
1,201 Views
Registered: ‎05-31-2017

Hi @mxdsgnl,

 

I have created a block design at my end and I followed the similar steps that are mentioned in the AR#60706 to simulate the sub IP present inside the BD. Although it shows the module as missing in the hierarchy window, I am able to run simulation without any errors. Can you please confirm if you are facing any errors while running simulation ?

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