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Visitor
Visitor
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Registered: ‎11-21-2019

single port ram ping-pang process

I instantiated two single ports of ram and implemented line caching in video processing through the ping-pong operation of these two ram.

The address entered cannot be picked while reading ram,So the value of the output does not correspond to the address of the input。

Can you tell me how to solve this problem?微信图片_20191211170606.png

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: single port ram ping-pang process

Hi @yongtang ,

 

Apologies I dont fully understand the description of the problem. 

There are some useful timing diagrams in the User Guide Pg13 onwards that maybe useful to you : https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf

 

If its not can you share more details on how the BRAMs are setup more details on the issues refering the relevant timing diagram from the UG.

 

Thanks,

Sandy

Thanks,
Sandy

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: single port ram ping-pang process

You might want to draw a timing diagram in your log book,
Remember that the BRAMs probably have output registers, which are needed for speed, which is I guess why you have a ping pong design,

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