12-11-2019 01:06 AM
I instantiated two single ports of ram and implemented line caching in video processing through the ping-pong operation of these two ram.
The address entered cannot be picked while reading ram，So the value of the output does not correspond to the address of the input。
Can you tell me how to solve this problem？
01-06-2020 08:37 AM
Hi @yongtang ,
Apologies I dont fully understand the description of the problem.
There are some useful timing diagrams in the User Guide Pg13 onwards that maybe useful to you : https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf
If its not can you share more details on how the BRAMs are setup more details on the issues refering the relevant timing diagram from the UG.
01-06-2020 08:59 AM