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Observer
Observer
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Registered: ‎12-06-2018

translate VHDL code to Verilog code

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I was translating VHDL code to Verilog. I did almost everything but when I saw variable in VHDL code and translated the way I thought it is getting error when synthesizing.

This is VHDL code

CONSTANT INIT_DELAY : STD_LOGIC_VECTOR(7 DOWNTO 0) := "01000010";
process(fsm_clk) variable counter : std_logic_vector(7 downto 0) := (others=>'0'); variable disable_rst : std_logic := '1'; begin if fsm_clk'event and fsm_clk='1' then if counter=INIT_DELAY then disable_init_rst := '0'; rst <= '1'; elsif disable_rst='1' then counter := counter + 1; rst <= '0'; end if; end if; end process;

and below thing is what I tried to translate.

 

parameter [7:0] INIT_DELAY = 8'b0100_0010;
reg [7:0] counter = 8'b0000_0000;
reg disable_rst = 1'b1;
always@ (posedge fsm_clk) begin if(counter==INIT_DELAY) begin disable_init_rst <= 1'b0; rst <= 1'b1; end else if(disable_rst==1'b1) begin counter <= counter + 1'b1; rst <= 1'b0; end end

the error message was

 

Signal counter[7] in unit top is connected to following multiple drivers:

I think translated code has nothing wrong but why having error.

Do I have to translate VHDL 'variable' in different way???

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Highlighted
1,070 Views
Registered: ‎01-08-2012

Your translation appears to be accurate.

One difference between VHDL variables and Verilog regs is that the VHDL variable is scoped so that it is only visible inside the process.  The Verilog reg has a scope that covers the entire module.

I suspect that you have other pieces of code that you have translated that also contained a variable called "counter" and this is giving you an error related to multiple drivers.  You will need to rename each of these counter regs so that they have unique names.

 

(N.B. a very literal translation would have used blocking assignments ("=" instead of "<=") for the regs that had been VHDL variables, however this makes no difference in practice for this particular code snippet.  Also, in general, you are usually better off using non-blocking assignments for Verilog regs.)

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Highlighted
1,071 Views
Registered: ‎01-08-2012

Your translation appears to be accurate.

One difference between VHDL variables and Verilog regs is that the VHDL variable is scoped so that it is only visible inside the process.  The Verilog reg has a scope that covers the entire module.

I suspect that you have other pieces of code that you have translated that also contained a variable called "counter" and this is giving you an error related to multiple drivers.  You will need to rename each of these counter regs so that they have unique names.

 

(N.B. a very literal translation would have used blocking assignments ("=" instead of "<=") for the regs that had been VHDL variables, however this makes no difference in practice for this particular code snippet.  Also, in general, you are usually better off using non-blocking assignments for Verilog regs.)

View solution in original post