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Adventurer
Adventurer
251 Views
Registered: ‎01-24-2018

use odelaye2 to delay data and clk in k7

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Q1:   How to implement output delay on data signal and clock signal 

I am confused about how to implement odelaye2 (fix mode) to delay data and clk in K7.

Below is my instantiation examples for both data signal and clk signal

Could you please to review if they are correct or nor?

// ODELAYE2 for Data signal delay
U_ODELAY : ODELAYE2
generic map (
CINVCTRL_SEL => "FALSE",
DELAY_src=> "ODATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 8,
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA")
port map (
CNTVALUEOUT => open,
DATAOUT => OQ,                       // output of ODELAYE2
C => '0',
CE => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => (others => '0'),
INC => '0',
LD => '0',
LDPIPEEN => '0',
ODATAIN => odelayin,            // the data input from OSERDESE2 
REGRST => '0');

 

// ODELAYE2 for CLK signal delay  (this output CLK signal's Freq is 200MHz)
U_ODELAY : ODELAYE2
generic map (
CINVCTRL_SEL => "FALSE",
DELAY_src=> "CLKIN",
HIGH_PERFORMANCE_MODE => "FALSE",
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 8,
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA")
port map (
CNTVALUEOUT => open,
DATAOUT => CLKOUT,                       // output of ODELAYE2, is going to hook up to OBUFTDS
C => '0',
CE => '0',
CINVCTRL => '0',
CLKIN => CLKIN,                       // clock from BUFG 
CNTVALUEIN => (others => '0'),
INC => '0',
LD => '0',
LDPIPEEN => '0',
ODATAIN => '0',        
REGRST => '0');

 

 

Q2 :  About the ODELAYE2's CLKIN's  description in UG471 page 135

The CLKIN input is driven from clock buffers (BUFIO, BUFG or BUFR). This clock is then
delayed by a value set to ODELAY_VALUE and output though the DATAOUT and output
buffer (OBUFT or OBUFTDS). When an IOBUF is used, the delayed clock can be routed
back to the FPGA logic.

 

Can I hook up the delayed clock to OBUFDS instead of OBUFTDS?  If not, Why the delayed clock can not be hook up to OBUFDS?

 

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
186 Views
Registered: ‎05-07-2019

Re: use odelaye2 to delay data and clk in k7

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Hi,

 

1.The way of output delay instantiation for DATA (fixed mode) is correct. Whereas in clock instantiation, the attribute SIGNAL_PATTERN should be CLOCK. This attribute is a concern for timing analysis mainly.

2. i) Using OBUFDS or OBUFTDS won’t be a problem, if you drive the delayed clock signal off the chip (not routed back to FPGA).

Give a try in VIVADO tool. If any problem in implementation, it will let you know by critical warning. I'm pretty sure it will not (while using OBUFDS).

Xilinx recommendation is to use ODDR to drive the clock off the chip.

ii) If you try to route the delayed clock signal back to the FPGA logic then you must use IOBUF.

 

Kind Regards,

Kasthuri

1 Reply
Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎05-07-2019

Re: use odelaye2 to delay data and clk in k7

Jump to solution

Hi,

 

1.The way of output delay instantiation for DATA (fixed mode) is correct. Whereas in clock instantiation, the attribute SIGNAL_PATTERN should be CLOCK. This attribute is a concern for timing analysis mainly.

2. i) Using OBUFDS or OBUFTDS won’t be a problem, if you drive the delayed clock signal off the chip (not routed back to FPGA).

Give a try in VIVADO tool. If any problem in implementation, it will let you know by critical warning. I'm pretty sure it will not (while using OBUFDS).

Xilinx recommendation is to use ODDR to drive the clock off the chip.

ii) If you try to route the delayed clock signal back to the FPGA logic then you must use IOBUF.

 

Kind Regards,

Kasthuri