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shashankupb
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Registered: ‎11-02-2015

viertex 7 GTX CDR circuit

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How does CDR works? I am little confused here... It self generates a toggling sequence and then it shows CDR is locked. When I send a continuous 1's or 0's clock will be lost and starts again with self generated toggling for clock detection. Why is it so? I was expecting CDR should be locked depending on the incoming sequence... why it generates self generated toggling sequence for locking purpose?

 

Thank you,

 

regards,

Shashank

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dwisehart
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Registered: ‎06-23-2013

No problem, Shashank.

 

UI just means unit interval.  One source clock or one bit for our discussion.

 

CID just means consecutive identical digits, which means the same bit level (high or low).

 

So you can have up to 512-1's or 512-0's in a row and the CDR should not lose the timing of the source clock.

 

Daniel

 

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dwisehart
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If you look at the GTX manual you will see that this "CDR" signal is an internal signal that is not meant to be interpreted as "locked/not-locked".  I have never heard a good explanation of what this output represents, but I have seen the same behavior you are describing.

 

Daniel

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shashankupb
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What is the worst case condition for recovering clock at the receiver? I mean how much long run of similar data it can tolerate?

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dwisehart
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That is in the data sheet for the part you are using.  The parameter is Run Length, and if this is your data sheet, it is on page 59.

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shashankupb
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@dwisehart Thank you! 

 

the data sheet which you have mentioned is the right one. But I didn't understand what it means: Runlength (CID) = 512 UI

could you please give me little description on this... What is CID and UI (units of issue) means?

 

regards,

Shashank

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dwisehart
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No problem, Shashank.

 

UI just means unit interval.  One source clock or one bit for our discussion.

 

CID just means consecutive identical digits, which means the same bit level (high or low).

 

So you can have up to 512-1's or 512-0's in a row and the CDR should not lose the timing of the source clock.

 

Daniel

 

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shashankupb
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@dwisehart Thank you again!

 

your information was helpful to me. Have a nice weekend!

 

regards,

Shashank

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shashankupb
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Hi @dwisehart 

 

I tried simulating on hardware and as well as on software... CDRlock is 1 even after 512 continuous identical bits, for be on safer side I have simulated with 576 continuous identical digits... its not working. 

 

Thank you.

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dwisehart
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The CDRlock output is not what you think it is.  Ignore it for your testing.  Just use actual data synchronization to determine if the hardware is working properly.

 

I have some doubts that the simulator tries to simulate the maximum CID run length.

 

Daniel

 

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shashankupb
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@dwisehart Hardware works fine even after 512 CID... When I simulate it for even long long run length of CID then track data is lost. 

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