07-28-2017 05:02 AM
07-28-2017 07:42 AM
The proper flow is to analyze the signal integrity of you design using a SI tool like Hyperlynx from Mentor (similar tools available from Cadence and others as well).
There is no limit on how fast the rise time may be, other than the constraints of the SI from overshoot and undershoot stay within limits in the data sheet, under the asbs max and recommended values (Tables 1 & 2).
08-01-2017 05:07 AM
The rise and fall time is determined not only by FPGA's output driver ability but also on capacitance loading (pcb trace, etc.). So the best approach to find out exact rise/fall times is running Signal Integrity (SI) simulations as per your board physics.
To do that you can download Virtex-7 IBIS model from the following link https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/virtex-series-fpgas.html