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2,665 Views
Registered: ‎07-28-2017

virtex7 rise/fall time

Hi,

 

Can anyone specify the input rise and fall time that the virtex 7 HP Bank can accept ?

 

Thank you.

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Scholar
Scholar
2,642 Views
Registered: ‎02-27-2008

s,

 

The proper flow is to analyze the signal integrity of you design using a SI tool like Hyperlynx from Mentor (similar tools available from Cadence and others as well).

 

There is no limit on how fast the rise time may be, other than the constraints of the SI from overshoot and undershoot stay within limits in the data sheet, under the asbs max and recommended values (Tables 1 & 2).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
2,595 Views
Registered: ‎08-01-2012

The rise and fall time is determined not only by FPGA's output driver ability but also on capacitance loading (pcb trace, etc.). So the best approach to find out exact rise/fall times is running Signal Integrity (SI) simulations as per your board physics. 

 

To do that you can download Virtex-7 IBIS model from the following link https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/virtex-series-fpgas.html 

 

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