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Contributor
Contributor
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Registered: ‎02-06-2019

vivado error in timming analysis

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There is a large setup violation of -2.258 ns between pwm_out_reg/C (clocked by sys_clk_pin) and pwm_out (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture

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Teacher
Teacher
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Registered: ‎07-09-2009

???

 

some background and you r design files as an attatchment please

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Teacher
Teacher
347 Views
Registered: ‎07-09-2009

???

 

some background and you r design files as an attatchment please

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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