what is the meaning of clock period in the figure ?

[microchip_zhang]

I have read the xapp224, and  do the clock period mean that the sampling time compared with the origin clock ? and why it is all the 0.75 clock period ?

and I do not understand the clock period in the figure , I think it is wrong ,

it should be 0.25  clock period in position 1 ,and should be 0.5 clock period in  position  2,right ?

[avrumw]

The numbers you are showing appear to be the requirement on the path between the flip-flop and the next flip-flop.

So looking at the second line, the first flip-flop is on the rising edge of CLK90 and the next one is on the rising edge of CLK; this is 0.75 of a clock period. All the remaining ones are on the rising edge of CLK so they are all 1 clock period.

On the third line, the first one is on the falling edge of CLK and the second one is on the rising edge of CLK90 - again 0.75 clock periods. The one after that is on the rising edge of CLK, so, again, 0.75 of a clock period.

The goal of this circuit is to oversample the input; the first flip-flop on each line samples the signal on four different phases; CLK rise, CLK90 rise, CLK fall (so 180 degrees) and CLK90 fall (so 270 degrees). From there, we have three requirements:

• Get all signals on to the CLK domain
• Never try and go from flop to flop in less than 0.75 of a clock period
  • For example, at reasonable clock periods, trying to go from CLK rise to CLK90 rise (0.25 of a clock period) could create timing violations
• End up with all the four samples at the same time
  • The first line samples at 0 degrees and has 4 clock periods of delay
  • The second line samples at 90 degrees and has 0.75+1+1=3.75 clocks of delay
  • The third line samples at 180 degrees and has 0.75+0.75+1+1=3.5 clocks of delay
  • The fourth line samples at 270 degrees and has 0.75+0.75+0.75+1=3.25 clocks of delay

Avrum

[avrumw]

By the way - this XAPP is really old. You don't need to (and shouldn't) do this in newer FPGAs.

In the 7 series and the Virtex-6, the ISERDES has a defined oversample mode - in essence this circuit is implemented inside the ISERDES. Take a look at UG471 in the section "OVERSAMPLE Interface Type". 

This mode no longer exists in UltraScale/UltraScale+. But you can still use the ISERDES... The "fast" side (CLK) of the ISERDES can be clocked at a very high rate. To do 4x oversampling of a signal, you just need to use the ISERDES in DDR mode with a clock that is 1/2 the rate that you want to sample at; so if you want to have 4 samples at 100MHz, you generate a 200MHz clock, use two clock buffers, one a BUFGCE_DIV in divide by two mode (to generate the 100MHz clock), and the other a BUFGCE to generate the 200MHz clock. Use the 200MHz clock to drive the ISERDES CLK input and the 100MHz clock for CLKDIV, and set the ISERDES to 4:1 mode (DDR). This would almost certainly be faster than trying to use fabric flip-flops with the above circuit.

And both of these solutions are better. In these solutions the input data is captured only by one cell - the ISERDES; you don't have to worry about routing skew between the data input and the four capture flip-flops.

Avrum

[microchip_zhang]

Thank you very much, and I still have a question ,

 but I can not upload the figure,so I post another one,

https://forums.xilinx.com/t5/Other-FPGA-Architecture/why-0-25-period-will-create-timing-violations/td-p/1209202