cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
8,205 Views
Registered: ‎07-13-2015

what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

Hi

 

I am using 3v high and 3v low as input sine wave i.e, mean of approximately zero .What should be the values for CONFIG_VOLTAGE and CFGBVS. I am getting correct results even when i set the CONFIG as VCC0 :: 3.3V or GND :: 1.8V

Which one should i exactly use ?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
13,652 Views
Registered: ‎08-01-2008

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution
On which port or you are applying on GPIO . Check the GPIO voltage level in the board product guide
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

0 Kudos
13 Replies
Highlighted
Xilinx Employee
Xilinx Employee
8,204 Views
Registered: ‎02-14-2014

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

Hello @hulk789,

 

You need to check page #33 from below UG to know steps to determine the proper CFGBVS pin settings

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,194 Views
Registered: ‎08-01-2012

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

CFGBVS only requires that the pin reach the expected signal switching level relative to Vcco_0. So CFGBVS = VCCO of Bank 0. Please refer http://www.xilinx.com/support/answers/57045.html for more details.

 

FYI:

I believe you are using 7-series device. In that case please refer http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf for more details.

 

The below are some related noting points with respect to your query.

 

  1. The 7-series FPGA IO pins are not meant for analog sin wave inputs.
  2. Configuration Banks Voltage Select CFGBVS determines the I/O voltage operating range and voltage tolerance for the dedicated configuration bank 0 and for the multi-function configuration pins in banks 14 and 15 in the Artix-7 and Kintex-7 families. CFGBVS selects the operating voltage for the dedicated bank 0 at all times in all 7 series devices. CFGBVS selects the operating voltage for the multi-function configuration banks 14 and 15 only during configuration. Connect CFGBVS High or Low per the bank voltage requirements. If the VCCO_0 supply for bank 0 is supplied with 2.5V or 3.3V, then the CFGBVS pin must be tied High (i.e. connected to VCCO_0). Tie CFGBVS to Low (i.e. connected to GND), only if the VCCO_0 for bank 0 is less than or equal to 1.8V. If used during configuration, banks 14 and 15 should match the VCCO level applied to bank 0. Caution! To avoid device damage, CFGBVS must be connected correctly to either VCCO_0 or GND. See Configuration Banks Voltage Select, page 32 for more information.
  3. The CFGBVS pin is not available on Virtex-7 HT devices. Virtex-7 HT devices support only 1.8V/1.5V operation for bank 0.
  4. The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0) or Low (GND) to set the configuration and JTAG I/O in banks 0, 14, and 15 for 3.3V/2.5V or 1.8V/1.5V operation, respectively. When CFGBVS is set to Low for 1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V (or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for configuration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V. See Configuration Banks Voltage Select, page 32 for further details.

 

 

 

 

 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Highlighted
Explorer
Explorer
8,178 Views
Registered: ‎07-13-2015

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

what does 1.8/3.3/1.5/2.5 represent the mean value or maximum/minimum value

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,152 Views
Registered: ‎08-01-2012

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

The 1.8/3.3/1.5/2.5V are  typical/ mean values

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,151 Views
Registered: ‎08-01-2008

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution
These represents voltage levels

1.8V, 3.3V 1.5V etc
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Explorer
Explorer
8,136 Views
Registered: ‎07-13-2015

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

can the mean value/voltage level be zero

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,133 Views
Registered: ‎08-01-2008

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution
No these are the voltage levels supported by the FPGA. I am reading your orginal thread in which you are asking about +- 3 volt. How are you applying sine way . Are you applying analog sine input . you must using ADC . check the ADC datasheet in details
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Explorer
Explorer
8,132 Views
Registered: ‎07-13-2015

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

i am directly appling sine wave from signal generator.

i am using xc7k325t board.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
13,653 Views
Registered: ‎08-01-2008

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution
On which port or you are applying on GPIO . Check the GPIO voltage level in the board product guide
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

0 Kudos
Highlighted
Explorer
Explorer
6,058 Views
Registered: ‎07-13-2015

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

Some on board circuitry to generate a square wave

0 Kudos
Highlighted
Scholar
Scholar
6,040 Views
Registered: ‎02-27-2008

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

h,

 

DO NOT DO THAT!

 

The absolute maximum ratings prohibit any voltage below ~ -0.5 volts.


You may destroy the input.  The +/- 3 volt signal must be conditioned to make it safe.

 

A series 100 ohm resistor, with a clamp diode to Vcco from the pin and the other end of the 100 ohm (same as the bank Vcco you use), and a clamp diode from ground to the input pin.

 

The IO standard you then use will not matter, as you have clamped the signal to the Vcco voltage for that IO pin.  You may use any single ended standard  and voltage that is convenient (LVCMOS 1.5, 1.8, 2.4, etc.).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Highlighted
Explorer
Explorer
6,033 Views
Registered: ‎07-13-2015

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

I have decresed the input voltage.Thanks for your suggestion 

0 Kudos
Highlighted
Scholar
Scholar
6,025 Views
Registered: ‎02-27-2008

Re: what should be the CONFIG_VOLTAGE and CFGBVS

Jump to solution

h,

 

If the generator has a 50 ohm output impedance, the diodes in the IO structure should clamp the voltage, and keep the device safe as well.  Keep the peak positive output voltage at or below the Vcco for the IO bank.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos