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Visitor
Visitor
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Registered: ‎01-16-2020

xczu2cgsfvc784's 100MHz clock

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Hello, experts.

 

I am a new user in FPGA world, starting work in Zynq UltraScla+ after little practice in Zedboard with Zynq7000.

 

In Zedboard, I could easily get design constraint for 100MHZ. Zedboard Hardware guide gives pinout (Y9) for desired clock.

 

In UltraScale+, specifically xczu2cgsfvc784, I have pinout files, which shows I/O bank 64,65,66 pins for PL for users. However, I can not decipher what is used for 100MHz clock based on either pin or pin Name (IO_L18N_T2U_N11_AD2N_66 or IO_L23P_T3U_N8_I2C_SCLK_6 don't give me much information).

 

I randomly tried K9 :IO_L23P_T3U_N8_I2C_SCLK_6 as global clock and it gave me this error message in the screenshotScreenshot (24).png

It complains that my pin assignment for global clock is incorrect or very dangerous.

I believe there must be document of which I/O pin in pinout file should be used as clock, or so.

In additon, I would need information for Voltage input for each pin as well.

Where are those information documented?

 

Thank you.

 

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Xilinx Employee
Xilinx Employee
188 Views
Registered: ‎08-13-2007

回复: xczu2cgsfvc784's 100MHz clock

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The naming convention can be a bit confusing if you haven't seen it before.

For ZU+ MPSoC, you can find it here:

https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf

table 1-5 pages 12-17 for rev v1.8.1

Cheers,

bt

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-25-2010

回复: xczu2cgsfvc784's 100MHz clock

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Hi

You need to use IO pins with GC, such as lO_L14N_T2L_N3_GC_65 with _GC.

 Voltage infor, please see HP/HR bank Table 1-77, in ug571:

https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

Thanks
Simon
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Highlighted
Visitor
Visitor
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Registered: ‎01-16-2020

回复: xczu2cgsfvc784's 100MHz clock

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Thank you for your message.

Indeed, I believe there is some code hidden in the pin name that I didn't know beforehand (such as GC).

Could I get a reference for a list of those codes ? such as what HDGC, AD, QBC, DBC, ....mean for Zynq?

 

Thank you

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Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎08-13-2007

回复: xczu2cgsfvc784's 100MHz clock

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The naming convention can be a bit confusing if you haven't seen it before.

For ZU+ MPSoC, you can find it here:

https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf

table 1-5 pages 12-17 for rev v1.8.1

Cheers,

bt

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