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Visitor fmartina
Visitor
1,381 Views
Registered: ‎03-06-2018

xil_io functions and cache coherency

Dear All,

 

I'm working on a Zynq 7000 device. 

In my project initialization I have to configure several IP registers in the PL using a GP AXI Master interface. Just image the simplest zynq project structure.

 

I did it a lot of times but I always had a doubt. When I use function like Xil_Out32(...)  Xil_In32(...) , should I flush/invalidate the cache?

 

I noticed in the past that avoiding these cache operations could causes problems like not effectively configured register etc. So then I always used those. 

 

The strange think is that if you look to, for example, the Xil_Out32(...) implementation you can see this code:

 

static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
}

 

In my opinion (that could be wrong of course), there is no cache care. I thought that the XStl_RegUpdate would do exactly what I need but this function is actually NOT implemented yet. 

What do you think? 

Should I flush/invalidate cache? Should I configure the MMU? Or the code works well also without other modifications?

 

Regards

 

Francesco

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4 Replies
Scholar hbucher
Scholar
1,437 Views
Registered: ‎03-22-2016

Re: xil_io functions and cache coherency

@fmartina Francesco

The standalone BSP will program the TLB such that only DDR will be cacheable. Other address regions (peripherals) will not so flushing the cache is unnecessary. Not to mention cache flushing can be extremely expensive, to the order of hundreds of cycles.

https://www.xilinx.com/Attachment/Changing_The_Cacheability_for_Memory.pdf

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Visitor fmartina
Visitor
1,352 Views
Registered: ‎03-06-2018

Re: xil_io functions and cache coherency

Now It's much much clearer.

Thank you a lot.

 

Regards

Visitor fmartina
Visitor
1,271 Views
Registered: ‎03-06-2018

Re: xil_io functions and cache coherency

Dear hbucher,

 

unfortunately I'm still having problem related to registers write/read.

I'm trying to configure an AXI quad SPI module (0x41E0_0000) and an AXI GPIO module (0x4120_0000).

 

The last week I wrote a simple custom driver based on Xil_io function and I used the cache invalidation/flush since I didn't know that the BSP configures the TLB. Furthermore I didn't need very high performance on SPI so the time required for those operation was tolerated. 

 

Today I'm reusing that driver and I deleted all the cache operation following your information. But the problem is that it does not work. I see clearly that the behaviour is corrupted by cache problems.

 

May you show me exactly where the TLB are configured in bsp?

 

I'm using an lwIP project template.

 

Regards

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Scholar hbucher
Scholar
1,263 Views
Registered: ‎03-22-2016

Re: xil_io functions and cache coherency

 
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zynq_translation_table.png
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