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Visitor
Visitor
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Registered: ‎02-19-2020

zc706 Clock Constraint & JTAG Operation at 3.3v

Hi,

I tried to use ZC706 board to generate a clock output through SMA.

I have programmed VADJ as 3.3V & connected a 3.3V ,30MHz frequency clock signal from external signal generator and used it as input to ZC706  & AD9744 DAC.

 As far as I understand, and from reading other posts in the forum, I could use USER_SMA_CLOCK_P (AD18) as input port for the single ended clock since VADJ_FPGA is compatible with 3.3V. USER_SMA_CLOCK_N (AD19) left unconnected .However, looking at the XDC listing given in zc706 data sheet, I saw only IOSTANDARD LVDS_25 for AD18. I tried to constrain it with LVCMOS33.

I have used the following clock pin constraint..

set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports user_clk_P]

 

I have connected user_clk_P to an ILA port. But it is not capturing clock signal. What would be the reason for this?

Can I use AD18 as single ended clock input port?  Is there another method for giving clock constraints at 3.3v?

 

I have modified the constraint file as:

set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports user_clk_P]

set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports user_clk_N]

 

Now I am getting DAC output..Then I tried to analyze DAC data & clock signals using ILA . But this ILA is not working..Vivado is showing an error message:

ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210251A55726. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. ERROR: [Labtools 27-55] Invalid index 0 passed to get Device in zc706.

I am using Digilent USB-to-JTAG interface U30.SW4 setting is 01. JTAG is exactly Xilinx_tcf /Digilent and frequency set to 15000000. 

How can this issue be resolved? I would like to know the JTAG operation at 3.3v VADJ in zc706…

 

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4 Replies
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Teacher
Teacher
269 Views
Registered: ‎07-09-2009

Re: zc706 Clock Constraint & JTAG Operation at 3.3v

lots of questions there, lets see what we can do,

 

Looking at the docs

https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf

 

page 38 says  USER_SMA_CLOCK_P  is differential LVDS, 

    but as you say, if you recompile the code to use a single ended input, then you could use a single ended input clock. As to voltage, you have seen the bit about voltages, but you might run into bank voltage rules. 

 

re connecting an ILA to the clock pin, how would that be able to capture a clock ? Assuming say 30 MHz clock on USER_SMA_CLOCK_P , then you would have to have a few hundred mhz sample clock on the ILA to hope to capture anything useful.

using the clock input single ended, you do not use differential termination. 

JTAg and voltage, 

   looking at page 33, 

       do you have the fmc bypass'd if your not using it ? and ensure your selecting the right JTAG with sw4 

first thing to do with JTAG is to get a scope and see what the JTAG signal looks like. 

 

 

 

 

     

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Highlighted
257 Views
Registered: ‎06-21-2017

Re: zc706 Clock Constraint & JTAG Operation at 3.3v

You did use a scope verify that your signal generator is not driving the clock input below ground, right?

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Highlighted
Visitor
Visitor
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Registered: ‎02-19-2020

Re: zc706 Clock Constraint & JTAG Operation at 3.3v

I have verified the signal generator output in CRO..

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Visitor
Visitor
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Registered: ‎02-19-2020

Re: zc706 Clock Constraint & JTAG Operation at 3.3v

Is it necessary to use 3.3v clock signal when VADJ =3.3v..Can I use single ended clock with LVCMOS because there is no LVDS_33?

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