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Registered: ‎09-22-2019

zynq fabric clock CPU clock

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As the subject, what is the different with  fabric clock and CPU clock?

and what are thery used for respectively?

Thank you!

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Registered: ‎01-22-2015

Re: zynq fabric clock CPU clock

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@chris0622 

The Software Development Kit (SDK) is used to develop software functions for the PS side of the Zynq.  Vivado HLS or Vivado HLx is used to develop hardware functions for the PL side of the Zynq.  So, clocks that you use in SDK would be considered clocks for the CPU (ie. the Zynq ARM core processor).

On the PL side of the Zynq, a clock usually enters the FPGA on a clock-capable pin and the code we write should route it immediately to a clock management tile (CMT) or clock buffer.  Both the CMT and the clock buffer place the clock into the clock tree.  Thereafter, we strive to write code for the PL side that keeps the clock in the clock tree. That is, we strive to write code that results in the clock being connected only to the clock-pin of components (eg. the C-pin of a digital register). 

However, some people write code that causes the clock to be routed to other pins of components.  So, for example, if you route a clock to the D-pin of a digital register then you have “pulled” the clock from the clock tree and are routing it through the fabric as a digital signal.  This fabric-routed version of the clock will suffer from delays and variations that the Xilinx tools have difficulty characterizing.  So, it you use the fabric routed clock to clock digital registers then the Xilinx tools (Vivado) will have trouble performing timing analysis on your design.

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Re: zynq fabric clock CPU clock

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@chris0622 

Everywhere in your Zynq FPGA you will find clocked logic (ie. a digital register receives the rising-edge of a clock and responds by sending 1-bit of data to another digital register).  However, your Zynq is divided into a PS and PL side.  So, the answer to your question (I think) is that a CPU clock is used on the PS side and a “fabric” clock is used on PL side. 

On the PL side, the word fabric refers to most of the circuits, which includes digital registers.  Clocks are usually routed through special circuits called the clock tree.  The clock tree has branches which allow clocks to reach into the fabric and clock the digitial registers.  Some people try to route clocks through the PL fabric, which is a bad idea because this can severely degrade operation of the PL clocked logic. 

Mark

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Re: zynq fabric clock CPU clock

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so do you mean that CPU clock works on sdk ? right?

but what does" Some people try to route clocks through the PL fabric, which is a bad idea because this can severely degrade operation of the PL clocked logic. " mean ?

Thank you!

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Registered: ‎01-22-2015

Re: zynq fabric clock CPU clock

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@chris0622 

The Software Development Kit (SDK) is used to develop software functions for the PS side of the Zynq.  Vivado HLS or Vivado HLx is used to develop hardware functions for the PL side of the Zynq.  So, clocks that you use in SDK would be considered clocks for the CPU (ie. the Zynq ARM core processor).

On the PL side of the Zynq, a clock usually enters the FPGA on a clock-capable pin and the code we write should route it immediately to a clock management tile (CMT) or clock buffer.  Both the CMT and the clock buffer place the clock into the clock tree.  Thereafter, we strive to write code for the PL side that keeps the clock in the clock tree. That is, we strive to write code that results in the clock being connected only to the clock-pin of components (eg. the C-pin of a digital register). 

However, some people write code that causes the clock to be routed to other pins of components.  So, for example, if you route a clock to the D-pin of a digital register then you have “pulled” the clock from the clock tree and are routing it through the fabric as a digital signal.  This fabric-routed version of the clock will suffer from delays and variations that the Xilinx tools have difficulty characterizing.  So, it you use the fabric routed clock to clock digital registers then the Xilinx tools (Vivado) will have trouble performing timing analysis on your design.

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Registered: ‎01-22-2015

Re: zynq fabric clock CPU clock

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@chris0622 

In Xilinx document PG082 (pg87), I find the sentence "PL side peripherals can be operated through a fabric clock (FCLK_CLK0…3). "   Is this where you found the words " fabric clock " ?

The words, "fabric clock", in PG082 refer to the PS-side generated clocks called FCLKs that are sometimes used for clocks on the PL-side.  Please see my reply <here> about using FCLKs to clock the PL-side of the Zynq.

Mark

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