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4,764 Views
Registered: ‎09-19-2017

1 second counter using VHDL

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
 
entity One_sec is
    port(
        rst, clk: in std_logic;
        start, stop: in std_logic;
        led_out: out std_logic
        );
end One_sec;
 
architecture behavioral of One_sec is
    type state_type is 
        (idle, led_on, led_off);
    signal c_state, next_state: state_type;
    signal counter: unsigned (12 downto 0);
    signal count_up: std_logic;
 
begin
    FSM_COMB: process(rst, clk)
    begin
        if (rst='0') then
            c_state <= idle;
            counter <= (others => '0');
        elsif rising_edge(clk) then
            c_state <= next_state;
         
            if (count_up ='1') then
                counter <= counter + 1;
            else
                counter <= (others => '0');
            end if;
        end if;    
    end process;           
 
    SEQFSM: process(c_state, counter, start, stop)
    begin
        count_up <= '0';
        led_out <= '0';
 
        case c_state is
            when idle =>
                if(start = '1') then
                    next_state <= idle;
                else
                    next_state <= led_on;
                end if;
                
            when led_on =>
                led_out <= '1';
                if(stop = '0') then
                    next_state <= idle;
                elsif(counter < 49999999) then
                    count_up <= '1';
                    next_state <= led_on;
                else
                    count_up <= '1';
                    next_state <= led_off;
                end if;
                
            when led_off =>
                if (stop ='0') then
                    next_state <= idle;
                elsif (counter < 99999999) then
                    count_up <= '1';
                    next_state <= led_off;
                else
                    next_state <= led_on;
                end if;
           
           when others =>
                next_state <= idle;
        end case;
   end process;
end behavioral;
 
 
 
The code above is the code that I created and modified some for fitting my board.
The FPGA board I'm using is XILINX NEXYS4 ARTIX-7.
I used 12-bit for register of 'counter' and divided clock into 100000000 since the internal clock is 100MHz.
However, when I programmed on the board, the led on this board did not blink once a second, but blink with way too short period.
I tried to change the value for dividing clock, but it did not work.
So, I want to get some pieces of advice about what I'm doing wrong.
Thanks.
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1 Solution

Accepted Solutions
Voyager
Voyager
6,852 Views
Registered: ‎06-24-2013

Re: 1 second counter using VHDL

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Hey ldw1red2@gmail.com,

 

What @u4223374 means is that you want to change your 13 bit counter ...

    signal counter: unsigned (12 downto 0);

... to at least a 27 bit counter ...

    signal counter: unsigned (26 downto 0);

... so that it actually can count up to 100 milion.

 

Note that it is better to define the counter as natural/integer instead of unsigned for your purpose ...

    signal counter: natural range 0 to 99999999 := 0;

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
10 Replies
Scholar u4223374
Scholar
4,759 Views
Registered: ‎04-26-2015

Re: 1 second counter using VHDL

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A 12-bit counter only lets you count to 4095.

 

For 100,000,000 you need 27-bit.

0 Kudos
4,755 Views
Registered: ‎09-19-2017

Re: 1 second counter using VHDL

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Oh, that's what I'm missing. 

Then, is there any way I can divide the clock into 100000000 using this board that has only 12-bit register.

 

Thanks.

0 Kudos
4,753 Views
Registered: ‎09-19-2017

Re: 1 second counter using VHDL

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Oh, that's what I'm missing.
Then, is there any way I can divide the clock into 100000000 using this board that has only 12-bit register.

Thanks.
0 Kudos
Voyager
Voyager
6,853 Views
Registered: ‎06-24-2013

Re: 1 second counter using VHDL

Jump to solution

Hey ldw1red2@gmail.com,

 

What @u4223374 means is that you want to change your 13 bit counter ...

    signal counter: unsigned (12 downto 0);

... to at least a 27 bit counter ...

    signal counter: unsigned (26 downto 0);

... so that it actually can count up to 100 milion.

 

Note that it is better to define the counter as natural/integer instead of unsigned for your purpose ...

    signal counter: natural range 0 to 99999999 := 0;

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
4,746 Views
Registered: ‎09-19-2017

Re: 1 second counter using VHDL

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I changed 12-bit to 27-bit, but it's still not showing 1 second blinking. I guess the board does not have enough bit register. Is there any possibilities that cause this problem?
0 Kudos
Voyager
Voyager
4,730 Views
Registered: ‎06-24-2013

Re: 1 second counter using VHDL

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Hey ldw1red2@gmail.com,

 

I changed 12-bit to 27-bit, but it's still not showing 1 second blinking.

While the code is certainly a little convoluted, it seems to work fine under the correct conditions.

 

I guess the board does not have enough bit register.

I can assure you, the board has more than enough registers for this purpose.

 

Is there any possibilities that cause this problem?

Most likely the input conditions are not met.

 

Your HDL code has one clock (clk) and three logic inputs (rst, start, stop).

Assuming that 'clk' is driven with a 100MHz signal, your 'rst' and 'stop' signals need to be high '1' and your 'start' signal must go low '0' for the LED to start blinking at 1Hz.

 

Here is a simulation of your code with reduced counter values (4/9) ...

led_sim.png

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
4,714 Views
Registered: ‎09-19-2017

Re: 1 second counter using VHDL

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I fixed it to work right thanks to you.
Thanks Herbert!
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Voyager
Voyager
4,710 Views
Registered: ‎06-24-2013

Re: 1 second counter using VHDL

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You're welcome!

 

All the best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
Scholar ronnywebers
Scholar
4,643 Views
Registered: ‎10-10-2014

Re: 1 second counter using VHDL

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hello @hpoetzl, you wrote 'Note that it is better to define the counter as natural/integer instead of unsigned for your purpose '

 

until now I don't use much 'integers' in VHDL, I always turn to unsigned or signed values. Would you mind explaining why integers are a better choice here?

 

I can see that a range is more readable, but is there any other advantage besides that? 

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Scholar u4223374
Scholar
2,381 Views
Registered: ‎04-26-2015

Re: 1 second counter using VHDL

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@ronnywebers

 

One advantage is that the tools can warn you if it goes out of range. If you've said that the range of a variable is 0 to 9999, and you set it to 12345, then there's clearly a mistake in the code. However, if you had specified it as an unsigned 14-bit value (smallest that can store that range) then the tools cannot recognize that a mistake has been made (as 12345 is a perfectly valid 14-bit value).