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Explorer
Explorer
3,338 Views
Registered: ‎03-31-2016

7-series GTX CML I/O standard issue

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Hello

 

Xilinx transceivers uses CML IOSTANDARD.

 

 

In xilinx 7-series example design, have fixed GTREFCLK location, but other pins not configured(txdata/rxdata)

 

In below I/O table, the txdata and rxdata pins aren't configured CML I/O standard.

 

How do i can configured CML I/O standard?

 

constraints.PNG

IO.PNG

1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
5,980 Views
Registered: ‎02-06-2013

Re: 7-series GTX CML I/O standard issue

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Hi

 

Only the serial transceiver pins need to be constrained(txp,txn,rxp and rxn),parallel data(txdata and rxdata will be interfaced internal to the FPGA and doesn't need any IO constraints)

 

They can be done by specifying the pins or the GT location as done in your case below(GTXE2_CHANNEL_X0Y4)

 

As it supports only one IO standard it will set to correct standard by default.

Regards,

Satish

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2 Replies
Xilinx Employee
Xilinx Employee
5,981 Views
Registered: ‎02-06-2013

Re: 7-series GTX CML I/O standard issue

Jump to solution

Hi

 

Only the serial transceiver pins need to be constrained(txp,txn,rxp and rxn),parallel data(txdata and rxdata will be interfaced internal to the FPGA and doesn't need any IO constraints)

 

They can be done by specifying the pins or the GT location as done in your case below(GTXE2_CHANNEL_X0Y4)

 

As it supports only one IO standard it will set to correct standard by default.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Explorer
Explorer
3,314 Views
Registered: ‎03-31-2016

Re: 7-series GTX CML I/O standard issue

Jump to solution

Thanks for your help!!

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