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Explorer
Explorer
12,271 Views
Registered: ‎12-21-2009

7-series internal cell structure

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Hi all,

 

Where can i get a documentation describing the internal structure of the 7-series slice. Like that for virtex-5 family where a slice contains four LUT6 and four registers in addition to carry chain logic and so on

 

Any help would be appreciated,

thanks in advance

 

Amr

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Xilinx Employee
Xilinx Employee
16,314 Views
Registered: ‎08-02-2007

Re: 7-series internal cell structure

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Amr,

 

Check out the CLB User Guide:

http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

 

Start on page 16, then immediately after you'll see some SLICEM/SLICEL diagrams.

 

Regards,

Jon

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Xilinx Employee
Xilinx Employee
16,315 Views
Registered: ‎08-02-2007

Re: 7-series internal cell structure

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Amr,

 

Check out the CLB User Guide:

http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

 

Start on page 16, then immediately after you'll see some SLICEM/SLICEL diagrams.

 

Regards,

Jon

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Explorer
Explorer
12,258 Views
Registered: ‎12-21-2009

Re: 7-series internal cell structure

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Thanks alot :)

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Explorer
Explorer
12,254 Views
Registered: ‎12-21-2009

Re: 7-series internal cell structure

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I have another question :

 

I downloaded the 7-series DS to see the Kintex-7 summary. In the product table the #Logic Cells column brought my attention. What does the Logic Cell stand for ? Because in the Virtex-5 DS i did not find this column in the product table and hence i can not compare clearly between available logic resources between a Virtex-5 and a Kintex-7.

I decided to read about the internal CLB of the 7-series because the only clear Info for logic resources to compare with Virtex-5 is the number of slices but this is not enough, I still need to know the internal CLB structure !

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Xilinx Employee
Xilinx Employee
12,240 Views
Registered: ‎08-02-2007

Re: 7-series internal cell structure

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Amr,

 

Its a confusing subject, but in it's basic sense it's an attempt to quantify the amount of logic in a device in a generic way so you can compare devices.  I believe the common definition is the a LUT and FF.  Unfortunately with modern FPGAs, there are so much more to them than just LUTs and FFs, it's sorta a convention that doesn't really describe a device very completely.

 

I'm probably not the best person to speak on the history/etc of logic cells, so I'll leave it up to others, but there have been a  a few threads on the subject that go into it...here's a starting point:

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Logic-cell-to-Gate-count/td-p/5459

 

-Jon

 

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Participant jsgray
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12,230 Views
Registered: ‎08-28-2009

Re: 7-series internal cell structure

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[EDIT: Correction: In this post, I incorrectly equated Xilinx logic cells counts in older Virtex devices to the count of 4-LUTs in those devices. RalfK kindly points out this mistake in his reply below. Oh well.]

 

 "Logic cells" used to have a real engineering utlility, a strong basis in reality, as a count of device primitives, but now I find it a less than useful throwback-to-history marketing fudge factor.

 

In the old days, Xilinx FPGAs used 4-input lookup tables (4-LUTs) and flip-flops. This was called a logic cell. If you were an expert FPGA designer, thinking in 4-LUTs, the move to #LCs as a capacity metric was a big improvement vs the synthetic guesstimate metric "# equivalent ASIC / system gates".

 

More recently (since Virtex-5 and Spartan-6), and throughout the new 7 Series FPGAs, Xilinx FPGAs use splittable 6-input lookup tables (6-LUTs). These are splittable in the sense that one 6-LUT can sometimes be used to implement two logic functions (for example, two separate functions of five common inputs).

 

Of course, a 6-LUT can cover a larger logic network than a 4-LUT. For example, it can take three 4-LUTs to implement a 4-1 multiplexer, but only one 6-LUT. It takes two 4-LUTs but only one 6-LUT to implement a 2-bit 2-1 mux.

 

How to account for this increased utility? Xilinx could have left behind last decade's 4-LUT-specific "logic cells" and moved to a more precise quantifier like "#6-LUTs". But they did not. Instead they (apparently) multiply the #6-LUTs by a factor that estimates an equivalent #4-LUTs and call that the "logic cell" count.

 

For example, the Virtex-7 2000T has 4*305,400 = ~1.2M 6-LUTs, but Xilinx calls it a 2 million logic cell device. Actually it calls it a 1,954,560 logic cell device, although it seems questionable engineering to state a made-up quantity to six significant digits. The trade press universally herald it as a 2 million logic cell device, but in reality there are no "logic cell" structures per se in there. Not 2 million, not 1.9 million. Indeed one can devise synthetic netlists that require 1.3 million 4-LUT logic cells that cannot be mapped to this device. This is not to take away anything from the technical tour-de-force that is the '2000T. "A rose by any other name would smell as sweet."

 

 

To answer your question, I would just ignore the "#logic cells" quantity as undependable competitive marketing fluff and compare #6-LUTs, #BRAMs, #DSPs, etc. The #6-LUTs is 4*#slices in Virtex-5, -6, and 7 Series devices; #slices is given in the respective data sheets.

 

http://www.fpgacpu.org/log/jan01.html#010116

http://www.fpgacpu.org/#021129

 

Xilinx Employee
Xilinx Employee
12,225 Views
Registered: ‎10-11-2007

Re: 7-series internal cell structure

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Nice view of history, but not quite correct.

 

In the olden days (Virtex, Virtex-E) we made a futile attempt to equal something (LUT, BRAMs, DDLs, etc) to gate array counts. Called it System Gates. But with the addition of  MGTs and a  processor even marketing was unable to come up with a number. So we dropped that. We actually also had something like Logic Gates early on in Virtex which was Logic Cells * 12 and thus implying that 12 Asic logic gates would roughly equal one FPGA gate (that is not counting the BRAM, etc. Purely logic).

 

As for Logic Cells,  up until V5, that was 1.125 * LUTs implying that we had some muxes and other stuff in the CLB accounting for some more logic than simply the LUT by itself. With the 6 input LUT that factor changed from 1.25 to 1.6.

 

End of history lesson.

Participant jsgray
Participant
12,220 Views
Registered: ‎08-28-2009

Re: 7-series internal cell structure

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Thank you, Ralf. You are quite correct. I had forgotten Xilinx's 1.125x multiplier on logic cells vs. 4-LUTs. So much for my argument about the sanctity of logic cell counts.

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Explorer
Explorer
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Registered: ‎12-21-2009

Re: 7-series internal cell structure

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I have a quite enough knowledge about the internal Virtex-5 slice structure specially the LUT and carry chain primitives. I could simply multiply the number of slices by 4 to get the number of LUT6 primitives but it was confusing when i found the #logic cells column, i thought Xilinx has added different logic primitives to the slice in the 7-series devices that will modify the claimed equation (#slices*4= #LUT6).

 

I hope that the data sheets be made compatible so that a user can choose between different solutions like FPGA Kits specially that most of the Kit providers now are providing Virtex-5 boards. For 7-series being introduced in some PCIe card solutions it makes me confused to select between say an xc5vlx330t device and an equivalent Kintex-7 FPGA with nearly the same number of slices. In such case i need a column listing #LUT6 and #Registers also. Not all users are experts about Xilinx CLB structure to be able to conclude and clear and a fair comparison between different solutions.

 

Thanks alot for you contribution

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