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1,205 Views
Registered: ‎04-24-2016

AXI Quad SPI core doesn't generate clock for SPI Flash memory

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Hello,

 

i'm working on partial reconfiguration project using kintex-7 xc7k160tfbg484-1 and vivado 2015.4. partial bitstreams files have to be stored into external SPI flash memory to be called during run time. AXI Quad SPI IP core (with disable startup primitive option) and STARTUPE2 instantiate are used as interface between FPGA and external SPI flash memory. PRC IP core and ICAPE2 instantiate  are used for reconfiguration process.

 

the problem is: there is no clock signal generated from AXI Quad SPI IP core output pin (sck_o) to the input pin (USRCCLK0) of STARTUPE2 instantiate. this means that external SPI flash memory will not work. How to generate this clock (SPI_clock)?

 

Note: in spite of there is no clock signal generated from AXI Quad SPI IP core to external flash memory, the PRC IP signals at run time shows that the re configurable module is loaded successfully (status register value : 00000107 as seen in the attachment) and some time output is as expected.

 

i attached a part of the top level module (for AXI Quad SPI IP core and STARTUPE2 instantiate) and the debug signals during run time.

could you please help me?

 

AXI Quad SPI Core Design.jpg
AXI Quad SPI Siganls.jpg
AXI Quad SPI Siganls2.jpg
ICAP signals.jpg
PRC IP Signals.jpg
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Xilinx Employee
Xilinx Employee
1,560 Views
Registered: ‎11-17-2008

Re: AXI Quad SPI core doesn't generate clock for SPI Flash memory

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Partial Reconfiguration over QSPI or sync-mode BPI interfaces are not officially supported in UltraScale devices.  The STARTUP primitive is not shielded from global signals so the SHUTDOWN event at the head of a partial bitstream turns off the CCLK generated through the STARTUP module as you have observed.  Other memory interfaces such as an AXI_EMC can be used to build a delivery path for partial bitstreams.  Or, there is a way to bypass the STARTUP clock but external board modifications are necssary -- PM me for more information.

 

This limitation has been fixed in UltraScale+ silicon and documentation will be updated now that verification has been completed.

 

As far as the PRC is concerned, it is looking at the amount of data transferred by counting clocks.  As long as it does not receive an AXI transaction error it will see that it has done its job correctly.

 

thanks,

david.

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2 Replies
Xilinx Employee
Xilinx Employee
1,561 Views
Registered: ‎11-17-2008

Re: AXI Quad SPI core doesn't generate clock for SPI Flash memory

Jump to solution

Partial Reconfiguration over QSPI or sync-mode BPI interfaces are not officially supported in UltraScale devices.  The STARTUP primitive is not shielded from global signals so the SHUTDOWN event at the head of a partial bitstream turns off the CCLK generated through the STARTUP module as you have observed.  Other memory interfaces such as an AXI_EMC can be used to build a delivery path for partial bitstreams.  Or, there is a way to bypass the STARTUP clock but external board modifications are necssary -- PM me for more information.

 

This limitation has been fixed in UltraScale+ silicon and documentation will be updated now that verification has been completed.

 

As far as the PRC is concerned, it is looking at the amount of data transferred by counting clocks.  As long as it does not receive an AXI transaction error it will see that it has done its job correctly.

 

thanks,

david.

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1,150 Views
Registered: ‎04-24-2016

Re: AXI Quad SPI core doesn't generate clock for SPI Flash memory

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Thanks david for your quick reply,

i think this FPGA board is 7-series not ultra-scale device, but the result is the same that there is no output clock. do you think it is possible to use AXI EMC ip core as interface with external SPI flash memory? or you mean that i have to use another external flash memory like async. BPI or MRAM flash memory?.

- in case of i have to use external BPI or MRAM flash memory that are not exist on this board, so how can i program it using JTAG? is there another way?

 

thanks in advance.

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