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Participant mwerner2000
Participant
11,261 Views
Registered: ‎06-05-2015

Artix-7 GTP RXPMARESETDONE not behaving as described in UG482 v1.7

Dear ladies and gentlemen,

 

I am trying to get the GTP to work. I am using the GTRXRESET workaround described in the manual and the core generated by the CORE generator. Simulation does not work as expected. When the GTRXRESET is asserted the RXPMARESETDONE goes low as expected. It goes high soon after, but there is no second falling edge, which leads a stuck FSM of the RX Reset sequencer, because it waits for this edge. I am using SIM_RESET_SPEEDUP = FALSE. Does anyone know what could cause this issue? Maybe I am not waiting long enough for the PMARESETDONE signal to go low again. Simulation ran for about 1 ms.

 

Sincerely,

M. Werner

 

GTPE2_channel_inst: GTPE2_CHANNEL
    generic map(
--_______________________ Simulation-Only Attributes ___________________

        SIM_RECEIVER_DETECT_PASS                =>      ("TRUE"),
        SIM_RESET_SPEEDUP                       =>      ("FALSE"), --("TRUE"),
        SIM_TX_EIDLE_DRIVE_LEVEL                =>      ("X"),
        SIM_VERSION                             =>      ("1.0"),
        

       ------------------RX Byte and Word Alignment Attributes---------------
        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
        ALIGN_COMMA_ENABLE                      =>     ("1111111111"),
        ALIGN_COMMA_WORD                        =>     (2),
        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
        ALIGN_MCOMMA_VALUE                      =>     ("1001111100"),
        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
        ALIGN_PCOMMA_VALUE                      =>     ("0110000011"),
        SHOW_REALIGN_COMMA                      =>     ("TRUE"),
        RXSLIDE_AUTO_WAIT                       =>     (7),
        RXSLIDE_MODE                            =>     ("PCS"),
        RX_SIG_VALID_DLY                        =>     (10),

       ------------------RX 8B/10B Decoder Attributes---------------
        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
        DEC_VALID_COMMA_ONLY                    =>     ("FALSE"),

       ------------------------RX Clock Correction Attributes----------------------
        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
        CLK_COR_MAX_LAT                         =>     (9),
        CLK_COR_MIN_LAT                         =>     (7),
        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
        CLK_COR_REPEAT_WAIT                     =>     (0),
        CLK_COR_SEQ_LEN                         =>     (1),
        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
        CLK_CORRECT_USE                         =>     ("FALSE"),
        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
        CLK_COR_SEQ_2_4                         =>     ("0000000000"),

       ------------------------RX Channel Bonding Attributes----------------------
        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
        CHAN_BOND_MAX_SKEW                      =>     (1),
        CHAN_BOND_SEQ_LEN                       =>     (1),
        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),

       ---------------------------RX Margin Analysis Attributes----------------------------
        ES_CONTROL                              =>     ("000000"),
        ES_ERRDET_EN                            =>     ("FALSE"),
        ES_EYE_SCAN_EN                          =>     ("FALSE"),
        ES_HORZ_OFFSET                          =>     (x"010"),
        ES_PMA_CFG                              =>     ("0000000000"),
        ES_PRESCALE                             =>     ("00000"),
        ES_QUALIFIER                            =>     (x"00000000000000000000"),
        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
        ES_VERT_OFFSET                          =>     ("000000000"),

       -------------------------FPGA RX Interface Attributes-------------------------
        RX_DATA_WIDTH                           =>     (20),

       ---------------------------PMA Attributes----------------------------
        OUTREFCLK_SEL_INV                       =>     ("11"),
        PMA_RSV                                 =>     (x"00000333"),
        PMA_RSV2                                =>     (x"00002040"),
        PMA_RSV3                                =>     ("00"),
        PMA_RSV4                                =>     ("0000"),
        RX_BIAS_CFG                             =>     ("0000111100110011"),
        DMONITOR_CFG                            =>     (x"000A00"),
        RX_CM_SEL                               =>     ("11"),
        RX_CM_TRIM                              =>     ("1010"),
        RX_DEBUG_CFG                            =>     ("00000000000000"),
        RX_OS_CFG                               =>     ("0000010000000"),
        TERM_RCAL_CFG                           =>     ("100001000010000"),
        TERM_RCAL_OVRD                          =>     ("000"),
        TST_RSV                                 =>     (x"00000000"),
        RX_CLK25_DIV                            =>     (5),
        TX_CLK25_DIV                            =>     (5),
        UCODEER_CLR                             =>     ('0'),

       ---------------------------PCI Express Attributes----------------------------
        PCS_PCIE_EN                             =>     ("FALSE"),

       ---------------------------PCS Attributes----------------------------
        PCS_RSVD_ATTR                           =>     (x"000000000000"),

       -------------RX Buffer Attributes------------
        RXBUF_ADDR_MODE                         =>     ("FAST"),
        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
        RXBUF_EN                                =>     ("FALSE"),
        RX_BUFFER_CFG                           =>     ("000000"),
        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
        RXBUFRESET_TIME                         =>     ("00001"),
        RXBUF_THRESH_OVFLW                      =>     (61),
        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
        RXBUF_THRESH_UNDFLW                     =>     (4),
        RXDLY_CFG                               =>     (x"001F"),
        RXDLY_LCFG                              =>     (x"030"),
        RXDLY_TAP_CFG                           =>     (x"0000"),
        RXPH_CFG                                =>     (x"C00002"),
        RXPHDLY_CFG                             =>     (x"084020"),
        RXPH_MONITOR_SEL                        =>     ("00000"),
        RX_XCLK_SEL                             =>     ("RXUSR"),
        RX_DDI_SEL                              =>     ("000000"),
        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),

       -----------------------CDR Attributes-------------------------

       --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008

       --For GTX only: Display Port, HBR2 -   set RXCDR_CFG=72'h038C008bff20200010
        RXCDR_CFG                               =>     (x"0000107FE206001041010"),
        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
        RXCDR_LOCK_CFG                          =>     ("001001"),

       -------------------RX Initialization and Reset Attributes-------------------
        RXCDRFREQRESET_TIME                     =>     ("00001"),
        RXCDRPHRESET_TIME                       =>     ("00001"),
        RXISCANRESET_TIME                       =>     ("00001"),
        RXPCSRESET_TIME                         =>     ("00001"),
        RXPMARESET_TIME                         =>     ("00011"),

       -------------------RX OOB Signaling Attributes-------------------
        RXOOB_CFG                               =>     ("0000110"),

       -------------------------RX Gearbox Attributes---------------------------
        RXGEARBOX_EN                            =>     ("FALSE"),
        GEARBOX_MODE                            =>     ("000"),

       -------------------------PRBS Detection Attribute-----------------------
        RXPRBS_ERR_LOOPBACK                     =>     ('0'),

       -------------Power-Down Attributes----------
        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
        PD_TRANS_TIME_TO_P2                     =>     (x"64"),

       -------------RX OOB Signaling Attributes----------
        SAS_MAX_COM                             =>     (64),
        SAS_MIN_COM                             =>     (36),
        SATA_BURST_SEQ_LEN                      =>     ("1111"),
        SATA_BURST_VAL                          =>     ("100"),
        SATA_EIDLE_VAL                          =>     ("100"),
        SATA_MAX_BURST                          =>     (8),
        SATA_MAX_INIT                           =>     (21),
        SATA_MAX_WAKE                           =>     (7),
        SATA_MIN_BURST                          =>     (4),
        SATA_MIN_INIT                           =>     (12),
        SATA_MIN_WAKE                           =>     (4),

       -------------RX Fabric Clock Output Control Attributes----------
        TRANS_TIME_RATE                         =>     (x"0E"),

       --------------TX Buffer Attributes----------------
        TXBUF_EN                                =>     ("FALSE"),
        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
        TXDLY_CFG                               =>     (x"001F"),
        TXDLY_LCFG                              =>     (x"030"),
        TXDLY_TAP_CFG                           =>     (x"0000"),
        TXPH_CFG                                =>     (x"0780"),
        TXPHDLY_CFG                             =>     (x"084020"),
        TXPH_MONITOR_SEL                        =>     ("00000"),
        TX_XCLK_SEL                             =>     ("TXUSR"),

       -------------------------FPGA TX Interface Attributes-------------------------
        TX_DATA_WIDTH                           =>     (20),

       -------------------------TX Configurable Driver Attributes-------------------------
        TX_DEEMPH0                              =>     ("000000"),
        TX_DEEMPH1                              =>     ("000000"),
        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
        TX_MAINCURSOR_SEL                       =>     ('0'),
        TX_DRIVE_MODE                           =>     ("DIRECT"),
        TX_MARGIN_FULL_0                        =>     ("1001110"),
        TX_MARGIN_FULL_1                        =>     ("1001001"),
        TX_MARGIN_FULL_2                        =>     ("1000101"),
        TX_MARGIN_FULL_3                        =>     ("1000010"),
        TX_MARGIN_FULL_4                        =>     ("1000000"),
        TX_MARGIN_LOW_0                         =>     ("1000110"),
        TX_MARGIN_LOW_1                         =>     ("1000100"),
        TX_MARGIN_LOW_2                         =>     ("1000010"),
        TX_MARGIN_LOW_3                         =>     ("1000000"),
        TX_MARGIN_LOW_4                         =>     ("1000000"),

       -------------------------TX Gearbox Attributes--------------------------
        TXGEARBOX_EN                            =>     ("FALSE"),

       -------------------------TX Initialization and Reset Attributes--------------------------
        TXPCSRESET_TIME                         =>     ("00001"),
        TXPMARESET_TIME                         =>     ("00001"),

       -------------------------TX Receiver Detection Attributes--------------------------
        TX_RXDETECT_CFG                         =>     (x"1832"),
        TX_RXDETECT_REF                         =>     ("100"),

       ------------------ JTAG Attributes ---------------
        ACJTAG_DEBUG_MODE                       =>     ('0'),
        ACJTAG_MODE                             =>     ('0'),
        ACJTAG_RESET                            =>     ('0'),

       ------------------ CDR Attributes ---------------
        CFOK_CFG                                =>     (x"49000040E80"),
        CFOK_CFG2                               =>     ("0100000"),
        CFOK_CFG3                               =>     ("0100000"),
        CFOK_CFG4                               =>     ('0'),
        CFOK_CFG5                               =>     (x"0"),
        CFOK_CFG6                               =>     ("0000"),
        RXOSCALRESET_TIME                       =>     ("00011"),
        RXOSCALRESET_TIMEOUT                    =>     ("00000"),

       ------------------ PMA Attributes ---------------
        CLK_COMMON_SWING                        =>     ('0'),
        RX_CLKMUX_EN                            =>     ('1'),
        TX_CLKMUX_EN                            =>     ('1'),
        ES_CLK_PHASE_SEL                        =>     ('0'),
        USE_PCS_CLK_PHASE_SEL                   =>     ('0'),
        PMA_RSV6                                =>     ('0'),
        PMA_RSV7                                =>     ('0'),

       ------------------ TX Configuration Driver Attributes ---------------
        TX_PREDRIVER_MODE                       =>     ('0'),
        PMA_RSV5                                =>     ('0'),
        SATA_PLL_CFG                            =>     ("VCO_3000MHZ"),

       ------------------ RX Fabric Clock Output Control Attributes ---------------
        RXOUT_DIV                               =>     (2),

       ------------------ TX Fabric Clock Output Control Attributes ---------------
        TXOUT_DIV                               =>     (2),

       ------------------ RX Phase Interpolator Attributes---------------
        RXPI_CFG0                               =>     ("000"),
        RXPI_CFG1                               =>     ('1'),
        RXPI_CFG2                               =>     ('1'),

       --------------RX Equalizer Attributes-------------
        ADAPT_CFG0                              =>     (x"00000"),
        RXLPMRESET_TIME                         =>     ("0001111"),
        RXLPM_BIAS_STARTUP_DISABLE              =>     ('0'),
        RXLPM_CFG                               =>     ("0110"),
        RXLPM_CFG1                              =>     ('0'),
        RXLPM_CM_CFG                            =>     ('0'),
        RXLPM_GC_CFG                            =>     ("111100010"),
        RXLPM_GC_CFG2                           =>     ("001"),
        RXLPM_HF_CFG                            =>     ("00001111110000"),
        RXLPM_HF_CFG2                           =>     ("01010"),
        RXLPM_HF_CFG3                           =>     ("0000"),
        RXLPM_HOLD_DURING_EIDLE                 =>     ('0'),
        RXLPM_INCM_CFG                          =>     ('1'),
        RXLPM_IPCM_CFG                          =>     ('0'),
        RXLPM_LF_CFG                            =>     ("000000001111110000"),
        RXLPM_LF_CFG2                           =>     ("01010"),
        RXLPM_OSINT_CFG                         =>     ("100"),

       ------------------ TX Phase Interpolator PPM Controller Attributes---------------
        TXPI_CFG0                               =>     ("00"),
        TXPI_CFG1                               =>     ("00"),
        TXPI_CFG2                               =>     ("00"),
        TXPI_CFG3                               =>     ('0'),
        TXPI_CFG4                               =>     ('0'),
        TXPI_CFG5                               =>     ("000"),
        TXPI_GREY_SEL                           =>     ('0'),
        TXPI_INVSTROBE_SEL                      =>     ('0'),
        TXPI_PPMCLK_SEL                         =>     ("TXUSRCLK2"),
        TXPI_PPM_CFG                            =>     (x"00"),
        TXPI_SYNFREQ_PPM                        =>     ("000"),

       ------------------ LOOPBACK Attributes---------------
        LOOPBACK_CFG                            =>     ('0'),
        PMA_LOOPBACK_CFG                        =>     ('0'),

       ------------------RX OOB Signalling Attributes---------------
        RXOOB_CLK_CFG                           =>     ("PMA"),

       ------------------TX OOB Signalling Attributes---------------
        TXOOB_CFG                               =>     ('0'),

       ------------------RX Buffer Attributes---------------
        RXSYNC_MULTILANE                        =>     ('0'),
        RXSYNC_OVRD                             =>     ('0'),
        RXSYNC_SKIP_DA                          =>     ('0'),

       ------------------TX Buffer Attributes---------------
        TXSYNC_MULTILANE                        =>     ('0'),
        TXSYNC_OVRD                             =>     ('1'),
        TXSYNC_SKIP_DA                          =>     ('0')


    )
    port map
    (
        --------------------------------- CPLL Ports -------------------------------
        GTRSVD                                  =>      "0000000000000000",
        PCSRSVDIN                               =>      "0000000000000000",
        TSTIN                                   =>      "11111111111111111111",
        ---------------------------- Channel - DRP Ports  --------------------------
        DRPADDR                                 =>      i_RXR_DRPADDR,
        DRPCLK                                  =>      DRP_clk_in,
        DRPDI                                   =>      i_RXR_DRPDI,
        DRPDO                                   =>      i_GTP_DRPDO,
        DRPEN                                   =>      i_RXR_DRPEN,
        DRPRDY                                  =>      i_GTP_DRPRDY,
        DRPWE                                   =>      i_RXR_DRPWE,
        ------------------------------- Clocking Ports -----------------------------
        RXSYSCLKSEL                             =>      "00",
        TXSYSCLKSEL                             =>      "00",
        ----------------- FPGA TX Interface Datapath Configuration  ----------------
        TX8B10BEN                               =>      '1',
        ------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
        PLL0CLK                                 =>      GTP_clk_in,
        PLL0REFCLK                              =>      GTP_ref_clk_in,
        PLL1CLK                                 =>      '0',
        PLL1REFCLK                              =>      '0',
        ------------------------------- Loopback Ports -----------------------------
        LOOPBACK                                =>      (others => '0'),
        ----------------------------- PCI Express Ports ----------------------------
        PHYSTATUS                               =>      open,
        RXRATE                                  =>      (others => '0'),
        RXVALID                                 =>      open,
        ----------------------------- PMA Reserved Ports ---------------------------
        PMARSVDIN3                              =>      '0',
        PMARSVDIN4                              =>      '0',
        ------------------------------ Power-Down Ports ----------------------------
        RXPD                                    =>      "00",
        TXPD                                    =>      "00",
        -------------------------- RX 8B/10B Decoder Ports -------------------------
        SETERRSTATUS                            =>      '0',
        --------------------- RX Initialization and Reset Ports --------------------
        EYESCANRESET                            =>      '0',
        RXUSERRDY                               =>      '1',
        -------------------------- RX Margin Analysis Ports ------------------------
        EYESCANDATAERROR                        =>      open,
        EYESCANMODE                             =>      '0',
        EYESCANTRIGGER                          =>      '0',
        ------------------------------- Receive Ports ------------------------------
        CLKRSVD0                                =>      '0',
        CLKRSVD1                                =>      '0',
        DMONFIFORESET                           =>      '0',
        DMONITORCLK                             =>      '0',
        RXPMARESETDONE                          =>      i_GTP_RXPMARESETDONE,
        SIGVALIDCLK                             =>      '0',
        ------------------------- Receive Ports - CDR Ports ------------------------
        RXCDRFREQRESET                          =>      '0',
        RXCDRHOLD                               =>      '0',
        RXCDRLOCK                               =>      open,
        RXCDROVRDEN                             =>      '0',
        RXCDRRESET                              =>      '0',
        RXCDRRESETRSV                           =>      '0',
        RXOSCALRESET                            =>      '0',
        RXOSINTCFG                              =>      "0010",
        RXOSINTDONE                             =>      open,
        RXOSINTHOLD                             =>      '0',
        RXOSINTOVRDEN                           =>      '0',
        RXOSINTPD                               =>      '0',
        RXOSINTSTARTED                          =>      open,
        RXOSINTSTROBE                           =>      '0',
        RXOSINTSTROBESTARTED                    =>      open,
        RXOSINTTESTOVRDEN                       =>      '0',
        ------------------- Receive Ports - Clock Correction Ports -----------------
        RXCLKCORCNT                             =>      open,
        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
        RX8B10BEN                               =>      '1',
        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
        std_ulogic_vector(RXDATA)               =>      i_GTX_RXDATA,
        RXUSRCLK                                =>      RX_usr_clk_in,
        RXUSRCLK2                               =>      RX_usr_clk_in,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        RXPRBSERR                               =>      open,
        RXPRBSSEL                               =>      (others => '0'),
        ------------------- Receive Ports - Pattern Checker ports ------------------
        RXPRBSCNTRESET                          =>      '0',
        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
        std_ulogic_vector(RXCHARISCOMMA)        =>      i_GTX_RXCHARISCOMMA,
        std_ulogic_vector(RXCHARISK)            =>      i_GTX_RXCHARISK,
        std_ulogic_vector(RXDISPERR)            =>      i_GTX_DISPERR,
        std_ulogic_vector(RXNOTINTABLE)         =>      i_GTX_NOTINTABLE,
        ------------------------ Receive Ports - RX AFE Ports ----------------------
        GTPRXN                                  =>      Data_n_in,
        GTPRXP                                  =>      Data_p_in,
        PMARSVDIN2                              =>      '0',
        PMARSVDOUT0                             =>      open,
        PMARSVDOUT1                             =>      open,
        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
        RXBUFRESET                              =>      '0',
        RXBUFSTATUS                             =>      open,
        RXDDIEN                                 =>      '1',
        RXDLYBYPASS                             =>      '0',
        RXDLYEN                                 =>      '0',
        RXDLYOVRDEN                             =>      '0',
        RXDLYSRESET                             =>      RX_DLY_reset_in,
        RXDLYSRESETDONE                         =>      RX_DLY_reset_done_out,
        RXPHALIGN                               =>      '0',
        RXPHALIGNDONE                           =>      i_GTP_RX_phase_align_done,
        RXPHALIGNEN                             =>      '0',
        RXPHDLYPD                               =>      '0',
        RXPHDLYRESET                            =>      '0',
        RXPHMONITOR                             =>      open,
        RXPHOVRDEN                              =>      '0',
        RXPHSLIPMONITOR                         =>      open,
        RXSTATUS                                =>      open,
        RXSYNCALLIN                             =>      i_GTP_RX_phase_align_done,
        RXSYNCDONE                              =>      open,
        RXSYNCIN                                =>      '0',
        RXSYNCMODE                              =>      '1',
        RXSYNCOUT                               =>      open,
        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
        RXBYTEISALIGNED                         =>      RX_byte_is_aligned_out,
        RXBYTEREALIGN                           =>      RX_byte_realign_out,
        RXCOMMADET                              =>      RX_comma_det_out,
        RXCOMMADETEN                            =>      '1',
        RXMCOMMAALIGNEN                         =>      '1',
        RXPCOMMAALIGNEN                         =>      '1',
        RXSLIDE                                 =>      '0',
        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
        RXCHANBONDSEQ                           =>      open,
        RXCHBONDEN                              =>      '0',
        RXCHBONDI                               =>      "0000",
        RXCHBONDLEVEL                           =>      (others => '0'),
        RXCHBONDMASTER                          =>      '0',
        RXCHBONDO                               =>      open,
        RXCHBONDSLAVE                           =>      '0',
        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
        RXCHANISALIGNED                         =>      open,
        RXCHANREALIGN                           =>      open,
        ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
        DMONITOROUT                             =>      open,
        RXADAPTSELTEST                          =>      (others => '0'),
        RXDFEXYDEN                              =>      '0',
        RXOSINTEN                               =>      '1',
        RXOSINTID0                              =>      (others => '0'),
        RXOSINTNTRLEN                           =>      '0',
        RXOSINTSTROBEDONE                       =>      open,
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
        RXLPMLFOVRDEN                           =>      '0',
        RXLPMOSINTNTRLEN                        =>      '0',
        -------------------- Receive Ports - RX Equailizer Ports -------------------
        RXLPMHFHOLD                             =>      '0', --RXLPMHFHOLD_IN,
        RXLPMHFOVRDEN                           =>      '0',
        RXLPMLFHOLD                             =>      '0', --RXLPMLFHOLD_IN,
        --------------------- Receive Ports - RX Equalizer Ports -------------------
        RXOSHOLD                                =>      '0',
        RXOSOVRDEN                              =>      '0',
        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
        RXRATEDONE                              =>      open,
        ----------- Receive Ports - RX Fabric Clock Output Control Ports  ----------
        RXRATEMODE                              =>      '0',
        --------------- Receive Ports - RX Fabric Output Control Ports -------------
        RXOUTCLK                                =>      i_GTX_rx_usr_clk,
        RXOUTCLKFABRIC                          =>      open,
        RXOUTCLKPCS                             =>      open,
        RXOUTCLKSEL                             =>      "010",
        ---------------------- Receive Ports - RX Gearbox Ports --------------------
        RXDATAVALID                             =>      open,
        RXHEADER                                =>      open,
        RXHEADERVALID                           =>      open,
        RXSTARTOFSEQ                            =>      open,
        --------------------- Receive Ports - RX Gearbox Ports  --------------------
        RXGEARBOXSLIP                           =>      '0',
        ------------- Receive Ports - RX Initialization and Reset Ports ------------
        GTRXRESET                               =>      i_RXR_GTRXRESET_OUT,
        RXLPMRESET                              =>      '0',
        RXOOBRESET                              =>      '0',
        RXPCSRESET                              =>      '0',
        RXPMARESET                              =>      '0',
        ------------------- Receive Ports - RX OOB Signaling ports -----------------
        RXCOMSASDET                             =>      open,
        RXCOMWAKEDET                            =>      open,
        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
        RXCOMINITDET                            =>      open,
        ------------------ Receive Ports - RX OOB signalling Ports -----------------
        RXELECIDLE                              =>      open,
        RXELECIDLEMODE                          =>      "11",
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
        RXPOLARITY                              =>      '0',
        -------------- Receive Ports -RX Initialization and Reset Ports ------------
        RXRESETDONE                             =>      i_GTP_RXRESETDONE,
        --------------------------- TX Buffer Bypass Ports -------------------------
        TXPHDLYTSTCLK                           =>      '0',
        ------------------------ TX Configurable Driver Ports ----------------------
        TXPOSTCURSOR                            =>      "00000",
        TXPOSTCURSORINV                         =>      '0',
        TXPRECURSOR                             =>      (others => '0'),
        TXPRECURSORINV                          =>      '0',
        -------------------- TX Fabric Clock Output Control Ports ------------------
        TXRATEMODE                              =>      '0',
        --------------------- TX Initialization and Reset Ports --------------------
        CFGRESET                                =>      '0',
        GTTXRESET                               =>      TX_reset_in,
        PCSRSVDOUT                              =>      open,
        TXUSERRDY                               =>      '1',
        ----------------- TX Phase Interpolator PPM Controller Ports ---------------
        TXPIPPMEN                               =>      '0',
        TXPIPPMOVRDEN                           =>      '0',
        TXPIPPMPD                               =>      '0',
        TXPIPPMSEL                              =>      '0',
        TXPIPPMSTEPSIZE                         =>      (others => '0'),
        ---------------------- Transceiver Reset Mode Operation --------------------
        GTRESETSEL                              =>      '0',
        RESETOVRD                               =>      '0',
        ------------------------------- Transmit Ports -----------------------------
        TXPMARESETDONE                          =>      open,
        ----------------- Transmit Ports - Configurable Driver Ports ---------------
        PMARSVDIN0                              =>      '0',
        PMARSVDIN1                              =>      '0',
        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
        TXDATA(31 downto 16)                    =>      (others => '0'),
        TXDATA(15 downto 0)                     =>      std_logic_vector(TX_data_in),
        TXUSRCLK                                =>      TX_usr_clk_in,
        TXUSRCLK2                               =>      TX_usr_clk_in,
        --------------------- Transmit Ports - PCI Express Ports -------------------
        TXELECIDLE                              =>      '0',
        TXMARGIN                                =>      (others => '0'),
        TXRATE                                  =>      (others => '0'),
        TXSWING                                 =>      '0',
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        TXPRBSFORCEERR                          =>      '0',
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
        TX8B10BBYPASS                           =>      (others => '0'),
        TXCHARDISPMODE                          =>      (others => '0'),
        TXCHARDISPVAL                           =>      (others => '0'),
        TXCHARISK(3 downto 2)                   =>      (others => '0'),
        TXCHARISK(1 downto 0)                   =>      std_logic_vector(TX_char_is_ctrl_in),
        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
        TXDLYBYPASS                             =>      '0',
        TXDLYEN                                 =>      TX_DLY_ena_in,
        TXDLYHOLD                               =>      '0',
        TXDLYOVRDEN                             =>      '0',
        TXDLYSRESET                             =>      TX_DLY_reset_in,
        TXDLYSRESETDONE                         =>      TX_DLY_reset_done_out,
        TXDLYUPDOWN                             =>      '0',
        TXPHALIGN                               =>      TX_phase_align_in,
        TXPHALIGNDONE                           =>      TX_phase_align_done_out,
        TXPHALIGNEN                             =>      '1',
        TXPHDLYPD                               =>      '0',
        TXPHDLYRESET                            =>      '0',
        TXPHINIT                                =>      TX_phase_init_in,
        TXPHINITDONE                            =>      TX_phase_init_done_out,
        TXPHOVRDEN                              =>      '0',
        ---------------------- Transmit Ports - TX Buffer Ports --------------------
        TXBUFSTATUS                             =>      open,
        ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
        TXSYNCALLIN                             =>      '0',
        TXSYNCDONE                              =>      open,
        TXSYNCIN                                =>      '0',
        TXSYNCMODE                              =>      '0',
        TXSYNCOUT                               =>      open,
        --------------- Transmit Ports - TX Configurable Driver Ports --------------
        GTPTXN                                  =>      Data_n_out,
        GTPTXP                                  =>      Data_p_out,
        TXBUFDIFFCTRL                           =>      "100",
        TXDEEMPH                                =>      '0',
        TXDIFFCTRL                              =>      "1000",
        TXDIFFPD                                =>      '0',
        TXINHIBIT                               =>      '0',
        TXMAINCURSOR                            =>      "0000000",
        TXPISOPD                                =>      '0',
        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
        TXOUTCLK                                =>      i_GTX_tx_usr_clk,
        TXOUTCLKFABRIC                          =>      open,
        TXOUTCLKPCS                             =>      open,
        TXOUTCLKSEL                             =>      "011",
        TXRATEDONE                              =>      open,
        --------------------- Transmit Ports - TX Gearbox Ports --------------------
        TXGEARBOXREADY                          =>      open,
        TXHEADER                                =>      (others => '0'),
        TXSEQUENCE                              =>      (others => '0'),
        TXSTARTSEQ                              =>      '0',
        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
        TXPCSRESET                              =>      '0',
        TXPMARESET                              =>      '0',
        TXRESETDONE                             =>      TX_reset_done_out,
        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
        TXCOMFINISH                             =>      open,
        TXCOMINIT                               =>      '0',
        TXCOMSAS                                =>      '0',
        TXCOMWAKE                               =>      '0',
        TXPDELECIDLEMODE                        =>      '0',
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
        TXPOLARITY                              =>      '0',
        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
        TXDETECTRX                              =>      '0',
        ------------------ Transmit Ports - pattern Generator Ports ----------------
        TXPRBSSEL                               =>      (others => '0')

    );
    
    
    ------------------------- Soft Fix for Production Silicon----------------------
    RX_reset_seq_inst :  gtp_transceiver_x2048_gtrxreset_seq
        port map(
            DRPCLK                              => DRP_clk_in,
            RST                                 => '0',
            GTRXRESET_IN                        => RX_reset_in,
            RXPMARESETDONE                      => i_GTP_RXPMARESETDONE,
            DRPDO                               => i_GTP_DRPDO,
            DRPRDY                              => i_GTP_DRPRDY,
            GTRXRESET_OUT                       => i_RXR_GTRXRESET_OUT,
            DRPADDR                             => i_RXR_DRPADDR      ,
            DRPDI                               => i_RXR_DRPDI        ,
            DRPEN                               => i_RXR_DRPEN        ,
            DRPWE                               => i_RXR_DRPWE        ,
            DRP_OP_DONE                         => RX_reset_done_out
        );
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3 Replies
Xilinx Employee
Xilinx Employee
11,232 Views
Registered: ‎02-06-2013

Re: Artix-7 GTP RXPMARESETDONE not behaving as described in UG482 v1.7

Hi

 

Which version of tool and core are you using?

 

Is this issue seen with 2015.4 also

Regards,

Satish

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Participant mwerner2000
Participant
11,224 Views
Registered: ‎06-05-2015

Re: Artix-7 GTP RXPMARESETDONE not behaving as described in UG482 v1.7

Dear Satish,

 

I am using Vivado 2015.3 atm. The Problem just resolved as I came back from lunch ^^ It does indeed take more than 1 ms for the CDR to lock as indicated by the data sheet. Is there any simulation attribute I could set to reduce this time? The SIM_RESET_SPEEDUP cannot be set to TRUE because the DRP workaround won't work with it. Maybe there is an attribute to accelerate the CDR lock time (in simulation only)?

 

Sincerely,

M. Werner

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Moderator
Moderator
11,204 Views
Registered: ‎02-16-2010

Re: Artix-7 GTP RXPMARESETDONE not behaving as described in UG482 v1.7

Here is the note from ug482.
The sequence above will simulate correctly if SIM_RESET_SPEEDUP is set to FALSE.
If SIM_RESET_SPEEDUP is set to TRUE, the above sequence should be bypassed.

If you bypass the sequence and set the SIM_RESET_SPEEDUP to TRUE, simulation can run faster. But you should get the DRP sequence back in operation for hardware testing.
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