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Visitor andypazdan
Visitor
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Registered: ‎08-16-2018

Artix-7. Kintex-7. Affiliation of VREF pins.

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Where Can I find information about which VREF pins belong to which DQS pins?
I ask becouse there are two VREF pins for one bank. I quess that one VREF pin supports two DQS pairs, and second VREF supports second two DQS pairs. But which? It may not be in numerical order, for example in Kintex-7 XC7K70T-1FBG484 where bank 16 have reduced number of pins (only 2 DQS pairs, instead of 4 pairs on another banks), but still have 2 VREF pins.

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Moderator
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Registered: ‎09-18-2014

Re: Artix-7. Kintex-7. Affiliation of VREF pins.

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Andypazdan,

 

VREF is an input reference voltage... Outputs don't need VREF. If you need to free up the VREF pins for user IO functionality either use Internal VREF or non VREF based standards. The latter is difficult since most memory interfaces uses VREF based standards.

 

 

Regards,

T

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Community Manager
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Registered: ‎08-30-2011

回复: Artix-7. Kintex-7. Affiliation of VREF pins.

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Hi @andypazdan

 

When Vref is required within an IO bank, the two Vref pins for the bank must be both used as Vref supply inputs.

 

 

 

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Visitor andypazdan
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Registered: ‎08-16-2018

回复: Artix-7. Kintex-7. Affiliation of VREF pins.

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Even when only one pair of DQS pins from one bank are used?

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Moderator
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Registered: ‎09-18-2014

Re: Artix-7. Kintex-7. Affiliation of VREF pins.

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Andypazdan,

 

 I quess that one VREF pin supports two DQS pairs, and second VREF supports second two DQS pairs. But which?

Where are you basing this from? You need to connect both Vref pins for a stable input reference. As far as I know the two VREF pins are internally biased together. So if you use one the other cannot be used as an user IO.  Are you looking to try to save a VREF pin so you can use it as an user IO? If so why not just use internal VREF if that was the case? 

 

https://www.xilinx.com/support/answers/42036.html

 

Regards,

T

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Visitor andypazdan
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Registered: ‎08-16-2018

Re: Artix-7. Kintex-7. Affiliation of VREF pins.

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@tenzinc wrote:

Where are you basing this from?


 

Sorry for my late answer.

It's just my guess, based on the fact that such a thing would be logical.
One pin - one signal.
Two pins for one signal could cause a short circuit if voltages connected to this pins were different.

 

I have another question about CKP/CKN signals.
Are VREF used for this pins?
CKP/CKN are outputs pins, but they should have proper common-mode voltage since DDR3 memory chip receiving this signals.
So are FPGA uses VREF to generate CKP/CKP, or use VREF only to receive from DQS pins?

I ask because I'm not sure if I need VREF on bank where I plan to generate CKP/CKN signal.

 

I want to free some pins, but I not able to free VREF pins becouse i plan to use DDR3 at high freguency (above 400MHz).

so I tried to free at least one of VREF pins. But if it is not possible, i have to try something else.

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Moderator
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Registered: ‎09-18-2014

Re: Artix-7. Kintex-7. Affiliation of VREF pins.

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Andypazdan,

 

VREF is an input reference voltage... Outputs don't need VREF. If you need to free up the VREF pins for user IO functionality either use Internal VREF or non VREF based standards. The latter is difficult since most memory interfaces uses VREF based standards.

 

 

Regards,

T

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