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Visitor marcio_moura
Visitor
9,189 Views
Registered: ‎03-12-2015

Artix 7 - XADC Vp/Vn Connection Problems

Hello,

 

I've been using the board Artix-7 in a project but I cannot connect the hardwired connections of the XADC - Vp and Vn - and make the board understand I am using them.

 

The strange thing is that I am using the constraint file provided by Diligent. Here is part of the XDC file related with the PMOD of the XADC.

(...)

##Pmod Header JXADC

#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
(...)

 

Anyways, anybody had this problem? I read all the post in the forums but I could not find a solution. Me and my professor we are trying to solve this has been almos three days, and I must get this working ASAP =(

 

Thanks, guys!

 

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12 Replies
Xilinx Employee
Xilinx Employee
9,183 Views
Registered: ‎04-16-2012

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hello,

 

Constraints seems like correct. Are you getting any error message or critical warnings with these XDC constraints?

And I suggest you to contact Digilent, since you had mentioned that the constraint file was provided by them.

 

Thanks,

Vinay

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Visitor marcio_moura
Visitor
9,176 Views
Registered: ‎03-12-2015

Re: Artix 7 - XADC Vp/Vn Connection Problems

Yes. I am getting the error in which "set property" is not done correctly. The error is like if there is an certain variable "X" in my constrain file that I am actually not using in my top level design. Thus, the variable that is in my top level design is being grounded.

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Xilinx Employee
Xilinx Employee
9,167 Views
Registered: ‎07-31-2012

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hi,

 

Please check with the digilent team in case their default constraints don't work. Check in the same version of the tool which they recommend.

 

however in any case, you can directly write the constraints in the XDC by replacing the constraints. Below is an example

 

set_property PACKAGE_PIN [get_property LOC [get_board_part_pins leds_8bits_TRI_O[1]]] [get_ports LEDS_n[1]]
set_property IOSTANDARD [get_property IOSTANDARD [get_board_part_pins leds_8bits_TRI_O[1]]] [get_ports LEDS_n[1]]

Much better you can open the design in Vivado and then assign the pins to the specific location in the Package Pins view.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Visitor marcio_moura
Visitor
9,155 Views
Registered: ‎03-12-2015

Re: Artix 7 - XADC Vp/Vn Connection Problems

How do I get to this Package View? I've opened the I/O planner after synthesizing, but I could not figure out how I do change the assignment of the pins. I actually deleted my constraing file for the Vp/Vn and I'm trying to place it manually. I can do this as I would do in Quartus? <Vivado sometimes is tricky 'cause I'm more used to work with quartus>.

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Xilinx Employee
Xilinx Employee
9,107 Views
Registered: ‎04-16-2012

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hello,

After opening synthesized netlist, click on Layout --> IO PinPlanning (Package view opens up).

Now select the ports and drag to them to the correct pins in the package view and click on save button to save the netlist.

Thanks,
Vinay
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Visitor marcio_moura
Visitor
9,090 Views
Registered: ‎03-12-2015

Re: Artix 7 - XADC Vp/Vn Connection Problems

Guys, thanks for the replies.

 

I tried to place my pins into the specific locations at the I/O package viewer and I got this error:

xadc_problem.png

 

It seems that It blocks me from placing VP/VN into the A15/A16 location. Someone knows to overcome this problem and if there is any option I can't disable vivado from blocking me to do this?

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Xilinx Employee
Xilinx Employee
9,064 Views
Registered: ‎07-31-2012

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hi,

 

Please check if your XADC module has any location constraints in the design which is conflicting with the pin constraints.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Visitor marcio_moura
Visitor
9,060 Views
Registered: ‎03-12-2015

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hello, 

 

My constraint file does not instantiate any AD from the board. Should I instantiate or just delete them? The strange thing is that either ways it does not work.

 

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Visitor marcio_moura
Visitor
9,033 Views
Registered: ‎03-12-2015

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hello,

 

I`ve solved my problem. Actually I might get confused before because the XADC is hardwired, which means that you should specify it in an specific location. Thanks guys.

Tags (1)
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Visitor marcio_moura
Visitor
5,463 Views
Registered: ‎03-12-2015

Re: Artix 7 - XADC Vp/Vn Connection Problems

Guys,

 

Someone can help me? I've connected the VP/VN in the top level. I'll post the pictures below and then explain my problem:

p1.png

Connection of the wrapper at the top level module.

p2.png

XADC connections - Using AUX2

p3.png

 

Well, the aux2 port input from the XADC is hardwired to the AD3 of the Nexys4 DDR. However, I'm not able to see any result from this input, even though I've conected the output of the XADC to some LEDs to see the result. The XADC works just fine, because I could receive data from it in a rate of 44 KHz approximately (using an FSM to control this rate) and I could put the sign on the LEDs through the audio jack port. I'm out of options here. Can you guys help me out with this? Ah, also, when I am programming the board, Vivado shows me an option to follow the voltage and the temperature at the XADC, but the voltage stays stable in 1V. 

 

Thanks!

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Observer kwame.kyere
Observer
1,604 Views
Registered: ‎02-24-2016

Re: Artix 7 - XADC Vp/Vn Connection Problems

Hello,

 

could you please elaborate on your answer. How do you define a specific location ?

I am having a similar problem. Thank you in advance.

Best regards, 

 

Afrifa

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Xilinx Employee
Xilinx Employee
1,596 Views
Registered: ‎09-05-2007

Re: Artix 7 - XADC Vp/Vn Connection Problems

I think the answer is that you do NOT attempt to constrain the locations of the analogue pins at all. The connections made to the VP/VN and VAUXP[15:0]/VAUXN[15:0] inputs on the XADC primitive can only come from the pins physically allocated to provide those analogue connections. As such, any pin constraints would only be trying to specify the ONLY pins that can be used anyway.

 

The XADC reference design provided in the PicoBlaze package includes 3 pairs of analogue inputs and the constraints file specifically does NOT constrain any of those pins with the connections to the XADC primitive selecting which analogue inputs are used and hence which pins on the device package are used.

https://www.xilinx.com/ipcenter/processor_central/picoblaze/member/

Ken Chapman
Principal Engineer, Xilinx UK
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